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srisc1.v
module srisc1(input clock, input reset, output reg [7:0] pc, output [31:0] ir); wire [31:0] da, db, dc; wire [4:0] ra, rb, rc; wire write_enable; // instantiate memory wire [7:0] next_pc; inst inst_cache( .address(next_pc), .clock(clock), .q(ir) ); assign next_pc = pc + 1'b1; always @(posedge clock or negedge reset) if (!reset) pc <= 8'hff; // so that next_pc starts at zero else pc <= next_pc; endmodule
inst.v
// megafunction wizard: %ROM: 1-PORT% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altsyncram // ============================================================ // File Name: inst.v // Megafunction Name(s): // altsyncram // // Simulation Library Files(s): // altera_mf // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2007 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module inst ( address, clock, q); input [7:0] address; input clock; output [31:0] q; wire [31:0] sub_wire0; wire [31:0] q = sub_wire0[31:0]; altsyncram altsyncram_component ( .clock0 (clock), .address_a (address), .q_a (sub_wire0), .aclr0 (1'b0), .aclr1 (1'b0), .address_b (1'b1), .addressstall_a (1'b0), .addressstall_b (1'b0), .byteena_a (1'b1), .byteena_b (1'b1), .clock1 (1'b1), .clocken0 (1'b1), .clocken1 (1'b1), .clocken2 (1'b1), .clocken3 (1'b1), .data_a ({32{1'b1}}), .data_b (1'b1), .eccstatus (), .q_b (), .rden_a (1'b1), .rden_b (1'b1), .wren_a (1'b0), .wren_b (1'b0)); defparam altsyncram_component.clock_enable_input_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.init_file = "isa1.mif", altsyncram_component.intended_device_family = "Cyclone II", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 256, altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.widthad_a = 8, altsyncram_component.width_a = 32, altsyncram_component.width_byteena_a = 1; endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" // Retrieval info: PRIVATE: AclrByte NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: Clken NUMERIC "0" // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "isa1.mif" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RegAddr NUMERIC "1" // Retrieval info: PRIVATE: RegOutput NUMERIC "0" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: SingleClock NUMERIC "1" // Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" // Retrieval info: PRIVATE: WidthAddr NUMERIC "8" // Retrieval info: PRIVATE: WidthData NUMERIC "32" // Retrieval info: PRIVATE: rden NUMERIC "0" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: INIT_FILE STRING "isa1.mif" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" // Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0] // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] // Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 // Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL inst.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL inst.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL inst.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL inst.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL inst_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL inst_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL inst_waveforms.html TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL inst_wave*.jpg FALSE // Retrieval info: LIB_FILE: altera_mf
fit.summary
Fitter Status : Successful - Thu Feb 14 10:59:22 2008 Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition Revision Name : srisc1 Top-level Entity Name : srisc1 Family : Cyclone II Device : EP2C35F672C6 Timing Models : Final Total logic elements : 16 / 33,216 ( < 1 % ) Total combinational functions : 16 / 33,216 ( < 1 % ) Dedicated logic registers : 8 / 33,216 ( < 1 % ) Total registers : 8 Total pins : 42 / 475 ( 9 % ) Total virtual pins : 0 Total memory bits : 8,192 / 483,840 ( 2 % ) Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 11.042 ns From : inst:inst_cache|altsyncram:altsyncram_component|altsyncram_6j71:auto_generated|ram_block1a18~porta_address_reg7 To : ir[18] From Clock : clock To Clock : -- Failed Paths : 0 Type : Clock Setup: 'clock' Slack : N/A Required Time : None Actual Time : Restricted to 260.01 MHz ( period = 3.846 ns ) From : pc[0]~reg0 To : inst:inst_cache|altsyncram:altsyncram_component|altsyncram_6j71:auto_generated|ram_block1a18~porta_address_reg7 From Clock : clock To Clock : clock Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Thu Feb 14 17:31:23 2008