wire active;
wire [5:0] op;
wire [6:0] fn;
wire [4:0] ra,rb,rd,shf;
// 1 + 4*5 + 7 + 6 = 34
assign IF_out = {active,shf,fn,op,rd,rb,ra};
assign {active,shf,fn,op,rd,rb,ra} = ID_in;
wire [5:0] control;
wire [1:0] muxc;
// 1 + 2*5 + 7 + 2*6 + 2 = 32
assign ID_out = {active,shf,op,fn,control,muxc,rd};
// 1 + 6 + 7 + 6 + 5 = 25
assign EX_out = {active, op, fn, control, rd};
module IF_stage(input [31:0] ir,
output [33:0] info, output [31:0] immedse);
wire [5:0] op;
reg [6:0] fn;
reg [4:0] ra,rb,rd;
// COMMON FIELDS
`define RT 20:16
`define RS 25:21
`define OP 31:26
// RFORMAT FIELDS
`define FN 5:0
`define SH 10:6
`define RD 15:11
// IFORMAT
`define IMM 15:0
wire [4:0] shf = ir[`SH];
assign op = ir[`OP];
assign immedse = {(ir[15]?16'hffff:16'h0000),ir[`IMM]};
always
begin
ra <= ir[`RS];
if (op>1)
begin
rd <= ir[`RT];
fn <= {1'b0,ir[`FN]};
rb <= 5'h0;
end
else if (op==6'b1)
begin
fn <= {1'b1,ir[`FN]};
rd <= 5'd0;
rb <= 5'd0;
end
else
begin
fn <= {1'b0,ir[`FN]};
rd <= ir[`RD];
rb <= ir[`RT];
end
end
wire active = 1'b1;
assign info = {active,shf,fn,op,rd,rb,ra};
endmodule
module ID_stage(input [33:0] ID_info, output [31:0] info);
wire active;
wire [5:0] op;
wire [6:0] fn;
wire [4:0] ra,rb,rd,shf;
assign {active,shf,fn,op,rd,rb,ra} = ID_info;
// instantiate r-format control unit
wire [5:0] rcontrol;
rformat unit1(
.fn(fn),
.control(rcontrol)
);
// instantiate i-format control unit
wire [5:0] icontrol;
wire [1:0] muxi;
iformat unit2(
.op(op),
.control(icontrol),
.muxc(muxc)
);
wire flag = (op==0);
wire [5:0] control = (flag? rcontrol: icontrol);
wire [1:0] muxc = (flag? 2'b00: muxi);
assign info = {active,op,fn,shf,control,muxc,rd};
endmodule
module EX_stage(
input [33:0] ID_info,
input [31:0] qa, qb, immedse,
output [18:0] info,
output [31:0] qd
);
wire active;
wire [5:0] op;
wire [6:0] fn;
wire [5:0] rd,shf;
wire [5:0] control;
wire [1:0] muxc;
assign {active,op,fn,shf,control,muxc, rd} = ID_info;
wire [31:0] dmuxi; // muxi output
muxi mux1(
.dst(dmuxi),
.b(qb),
.immedse(immedse),
.control(muxc)
);
wire [31:0] dalu; // alu output
wire zero, ovfl;
alu my_alu(
.a(qa),
.b(dmuxi),
.control(control[3:0]),
.c(dalu)
);
assign qd = dalu;
assign info = {active, op, fn, rd};
endmodule
module MEM_stage(
input [33:0] EX_info,
output [18:0] MEM,info,
input [31:0] qd, qm,
output [31:0] qe
);
wire active;
wire [5:0] op;
wire [6:0] fn;
wire [5:0] rd,shf;
wire [5:0] control;
wire [1:0] muxc;
assign {active,op,fn,shf,control,muxc, rd} = EX_info;
assign qe = qd;
assign info = {active, op, fn, rd};
endmodule
Maintained by John Loomis, last updated 23 April 2012