Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
     Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
     Info: Processing started: Mon Apr 09 13:42:45 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mrisc1 -c mrisc1
Info: Found 1 design units, including 1 entities, in source file rom1.v
     Info: Found entity 1: rom1
Info: Found 1 design units, including 1 entities, in source file alu.v
     Info: Found entity 1: alu
Info: Found 1 design units, including 1 entities, in source file iformat.v
     Info: Found entity 1: iformat
Info: Found 1 design units, including 1 entities, in source file mrisc1.v
     Info: Found entity 1: mrisc1
Info: Found 1 design units, including 1 entities, in source file muxi.v
     Info: Found entity 1: muxi
Info: Found 1 design units, including 1 entities, in source file reg_file.v
     Info: Found entity 1: reg_file
Info: Found 1 design units, including 1 entities, in source file rformat.v
     Info: Found entity 1: rformat
Info: Found 1 design units, including 1 entities, in source file inst.v
     Info: Found entity 1: inst
Info: Found 1 design units, including 1 entities, in source file IF_stage.v
     Info: Found entity 1: IF_stage
Info: Found 1 design units, including 1 entities, in source file ID_stage.v
     Info: Found entity 1: ID_stage
Info: Found 1 design units, including 1 entities, in source file EX_stage.v
     Info: Found entity 1: EX_stage
Info: Elaborating entity "mrisc1" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at mrisc1.v(42): object "immedse_old" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at mrisc1.v(43): object "jump_target" assigned a value but never read
Info: Elaborating entity "rom1" for hierarchy "rom1:inst_cache"
Warning (10850): Verilog HDL warning at rom1.v(23): number of words (15) in memory file does not match the number of elements in the address range [0:255]
Warning (10030): Net "rom.data_a[31]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[30]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[29]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[28]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[27]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[26]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[25]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[24]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[23]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[22]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[21]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[20]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[19]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[18]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[17]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[16]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[15]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[14]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[13]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[12]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[11]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[10]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[9]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[8]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[7]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[6]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[5]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[4]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[3]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[2]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[1]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.data_a[0]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.waddr_a[7]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.waddr_a[6]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.waddr_a[5]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.waddr_a[4]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.waddr_a[3]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.waddr_a[2]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.waddr_a[1]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.waddr_a[0]" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "rom.we_a" at rom1.v(13) has no driver or initial value, using a default initial value '0'
Info: Elaborating entity "reg_file" for hierarchy "reg_file:regs"
Info: Elaborating entity "IF_stage" for hierarchy "IF_stage:stage1"
Info: Elaborating entity "ID_stage" for hierarchy "ID_stage:stage2"
Warning (10036): Verilog HDL or VHDL warning at ID_stage.v(6): object "ra" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at ID_stage.v(6): object "rb" assigned a value but never read
Warning (10858): Verilog HDL warning at ID_stage.v(19): object muxi used but never assigned
Warning (10030): Net "muxi[1]" at ID_stage.v(19) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "muxi[0]" at ID_stage.v(19) has no driver or initial value, using a default initial value '0'
Info: Elaborating entity "rformat" for hierarchy "ID_stage:stage2|rformat:unit1"
Info: Elaborating entity "iformat" for hierarchy "ID_stage:stage2|iformat:unit2"
Info: Elaborating entity "EX_stage" for hierarchy "EX_stage:stage3"
Warning (10036): Verilog HDL or VHDL warning at EX_stage.v(10): object "shf" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at EX_stage.v(36): truncated value with size 20 to match size of target (19)
Info: Elaborating entity "muxi" for hierarchy "EX_stage:stage3|muxi:mux1"
Info: Elaborating entity "alu" for hierarchy "EX_stage:stage3|alu:my_alu"
Info: Inferred 1 megafunctions from design logic
     Info: Inferred altsyncram megafunction from the following design logic: "rom1:inst_cache|rom~0" 
          Info: Parameter OPERATION_MODE set to ROM
          Info: Parameter WIDTH_A set to 32
          Info: Parameter WIDTHAD_A set to 8
          Info: Parameter NUMWORDS_A set to 256
          Info: Parameter OUTDATA_REG_A set to UNREGISTERED
          Info: Parameter ADDRESS_ACLR_A set to NONE
          Info: Parameter OUTDATA_ACLR_A set to NONE
          Info: Parameter INDATA_ACLR_A set to NONE
          Info: Parameter WRCONTROL_ACLR_A set to NONE
          Info: Parameter RAM_BLOCK_TYPE set to AUTO
          Info: Parameter INIT_FILE set to db/mrisc1.ram0_rom1_3af053.hdl.mif
Info: Elaborated megafunction instantiation "rom1:inst_cache|altsyncram:rom_rtl_0"
Info: Instantiated megafunction "rom1:inst_cache|altsyncram:rom_rtl_0" with the following parameter:
     Info: Parameter "OPERATION_MODE" = "ROM"
     Info: Parameter "WIDTH_A" = "32"
     Info: Parameter "WIDTHAD_A" = "8"
     Info: Parameter "NUMWORDS_A" = "256"
     Info: Parameter "OUTDATA_REG_A" = "UNREGISTERED"
     Info: Parameter "ADDRESS_ACLR_A" = "NONE"
     Info: Parameter "OUTDATA_ACLR_A" = "NONE"
     Info: Parameter "INDATA_ACLR_A" = "NONE"
     Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
     Info: Parameter "RAM_BLOCK_TYPE" = "AUTO"
     Info: Parameter "INIT_FILE" = "db/mrisc1.ram0_rom1_3af053.hdl.mif"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6781.tdf
     Info: Found entity 1: altsyncram_6781
Warning: Memory Initialization File or Hexadecimal (Intel-Format) File "mrisc1.ram0_rom1_3af053.hdl.mif" contains "don't care" values -- overwriting them with 0s
Warning: Memory Initialization File or Hexadecimal (Intel-Format) File "mrisc1.ram0_rom1_3af053.hdl.mif" contains "don't care" values -- overwriting them with 0s
Warning: 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
     Warning (13410): Pin "results[0]" is stuck at GND
     Warning (13410): Pin "results[1]" is stuck at GND
     Warning (13410): Pin "results[2]" is stuck at GND
     Warning (13410): Pin "results[3]" is stuck at GND
     Warning (13410): Pin "results[4]" is stuck at GND
     Warning (13410): Pin "results[5]" is stuck at GND
     Warning (13410): Pin "results[6]" is stuck at GND
     Warning (13410): Pin "results[7]" is stuck at GND
     Warning (13410): Pin "results[8]" is stuck at GND
     Warning (13410): Pin "results[9]" is stuck at GND
     Warning (13410): Pin "results[10]" is stuck at GND
     Warning (13410): Pin "results[11]" is stuck at GND
     Warning (13410): Pin "results[12]" is stuck at GND
     Warning (13410): Pin "results[13]" is stuck at GND
     Warning (13410): Pin "results[14]" is stuck at GND
     Warning (13410): Pin "results[15]" is stuck at GND
     Warning (13410): Pin "results[16]" is stuck at GND
     Warning (13410): Pin "results[17]" is stuck at GND
     Warning (13410): Pin "results[18]" is stuck at GND
     Warning (13410): Pin "results[19]" is stuck at GND
     Warning (13410): Pin "results[20]" is stuck at GND
     Warning (13410): Pin "results[21]" is stuck at GND
     Warning (13410): Pin "results[22]" is stuck at GND
     Warning (13410): Pin "results[23]" is stuck at GND
     Warning (13410): Pin "results[24]" is stuck at GND
     Warning (13410): Pin "results[25]" is stuck at GND
     Warning (13410): Pin "results[26]" is stuck at GND
     Warning (13410): Pin "results[27]" is stuck at GND
     Warning (13410): Pin "results[28]" is stuck at GND
     Warning (13410): Pin "results[29]" is stuck at GND
     Warning (13410): Pin "results[30]" is stuck at GND
     Warning (13410): Pin "results[31]" is stuck at GND
Info: Generated suppressed messages file C:/usr/projects/mrisc1/mrisc1.map.smsg
Info: Implemented 122 device resources after synthesis - the final resource count might be different
     Info: Implemented 2 input pins
     Info: Implemented 72 output pins
     Info: Implemented 16 logic cells
     Info: Implemented 32 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 87 warnings
     Info: Peak virtual memory: 180 megabytes
     Info: Processing ended: Mon Apr 09 13:43:00 2012
     Info: Elapsed time: 00:00:15
     Info: Total CPU time (on all processors): 00:00:04
Info: *******************************************************************
Info: Running Quartus II Fitter
     Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
     Info: Processing started: Mon Apr 09 13:43:12 2012
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off mrisc1 -c mrisc1
Info: Selected device EP2C35F672C6 for design "mrisc1"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning: Feature LogicLock is not available with your current license
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
     Info: Device EP2C50F672C6 is compatible
     Info: Device EP2C70F672C6 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
     Info: Pin ~ASDO~ is reserved at location E3
     Info: Pin ~nCSO~ is reserved at location D3
     Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 74 pins of 74 total pins
     Info: Pin pc[0] not assigned to an exact location on the device
     Info: Pin pc[1] not assigned to an exact location on the device
     Info: Pin pc[2] not assigned to an exact location on the device
     Info: Pin pc[3] not assigned to an exact location on the device
     Info: Pin pc[4] not assigned to an exact location on the device
     Info: Pin pc[5] not assigned to an exact location on the device
     Info: Pin pc[6] not assigned to an exact location on the device
     Info: Pin pc[7] not assigned to an exact location on the device
     Info: Pin ir[0] not assigned to an exact location on the device
     Info: Pin ir[1] not assigned to an exact location on the device
     Info: Pin ir[2] not assigned to an exact location on the device
     Info: Pin ir[3] not assigned to an exact location on the device
     Info: Pin ir[4] not assigned to an exact location on the device
     Info: Pin ir[5] not assigned to an exact location on the device
     Info: Pin ir[6] not assigned to an exact location on the device
     Info: Pin ir[7] not assigned to an exact location on the device
     Info: Pin ir[8] not assigned to an exact location on the device
     Info: Pin ir[9] not assigned to an exact location on the device
     Info: Pin ir[10] not assigned to an exact location on the device
     Info: Pin ir[11] not assigned to an exact location on the device
     Info: Pin ir[12] not assigned to an exact location on the device
     Info: Pin ir[13] not assigned to an exact location on the device
     Info: Pin ir[14] not assigned to an exact location on the device
     Info: Pin ir[15] not assigned to an exact location on the device
     Info: Pin ir[16] not assigned to an exact location on the device
     Info: Pin ir[17] not assigned to an exact location on the device
     Info: Pin ir[18] not assigned to an exact location on the device
     Info: Pin ir[19] not assigned to an exact location on the device
     Info: Pin ir[20] not assigned to an exact location on the device
     Info: Pin ir[21] not assigned to an exact location on the device
     Info: Pin ir[22] not assigned to an exact location on the device
     Info: Pin ir[23] not assigned to an exact location on the device
     Info: Pin ir[24] not assigned to an exact location on the device
     Info: Pin ir[25] not assigned to an exact location on the device
     Info: Pin ir[26] not assigned to an exact location on the device
     Info: Pin ir[27] not assigned to an exact location on the device
     Info: Pin ir[28] not assigned to an exact location on the device
     Info: Pin ir[29] not assigned to an exact location on the device
     Info: Pin ir[30] not assigned to an exact location on the device
     Info: Pin ir[31] not assigned to an exact location on the device
     Info: Pin results[0] not assigned to an exact location on the device
     Info: Pin results[1] not assigned to an exact location on the device
     Info: Pin results[2] not assigned to an exact location on the device
     Info: Pin results[3] not assigned to an exact location on the device
     Info: Pin results[4] not assigned to an exact location on the device
     Info: Pin results[5] not assigned to an exact location on the device
     Info: Pin results[6] not assigned to an exact location on the device
     Info: Pin results[7] not assigned to an exact location on the device
     Info: Pin results[8] not assigned to an exact location on the device
     Info: Pin results[9] not assigned to an exact location on the device
     Info: Pin results[10] not assigned to an exact location on the device
     Info: Pin results[11] not assigned to an exact location on the device
     Info: Pin results[12] not assigned to an exact location on the device
     Info: Pin results[13] not assigned to an exact location on the device
     Info: Pin results[14] not assigned to an exact location on the device
     Info: Pin results[15] not assigned to an exact location on the device
     Info: Pin results[16] not assigned to an exact location on the device
     Info: Pin results[17] not assigned to an exact location on the device
     Info: Pin results[18] not assigned to an exact location on the device
     Info: Pin results[19] not assigned to an exact location on the device
     Info: Pin results[20] not assigned to an exact location on the device
     Info: Pin results[21] not assigned to an exact location on the device
     Info: Pin results[22] not assigned to an exact location on the device
     Info: Pin results[23] not assigned to an exact location on the device
     Info: Pin results[24] not assigned to an exact location on the device
     Info: Pin results[25] not assigned to an exact location on the device
     Info: Pin results[26] not assigned to an exact location on the device
     Info: Pin results[27] not assigned to an exact location on the device
     Info: Pin results[28] not assigned to an exact location on the device
     Info: Pin results[29] not assigned to an exact location on the device
     Info: Pin results[30] not assigned to an exact location on the device
     Info: Pin results[31] not assigned to an exact location on the device
     Info: Pin clock not assigned to an exact location on the device
     Info: Pin reset not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Automatically promoted node clock (placed in PIN P2 (CLK2, LVDSCLK1p, Input))
     Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node reset (placed in PIN P1 (CLK3, LVDSCLK1n, Input))
     Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1
Info: Starting register packing
Info: Finished register packing
     Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
     Info: Number of I/O pins in group: 72 (unused VREF, 3.3V VCCIO, 0 input, 72 output, 0 bidirectional)
          Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
     Info: Statistics of I/O banks
          Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  62 pins available
          Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  57 pins available
          Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  56 pins available
          Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  58 pins available
          Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  65 pins available
          Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  58 pins available
          Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  58 pins available
          Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  56 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:04
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to memory delay of 2.666 ns
     Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y12; Fanout = 3; REG Node = 'pc[0]~reg0'
     Info: 2: + IC(0.455 ns) + CELL(0.414 ns) = 0.869 ns; Loc. = LAB_X12_Y12; Fanout = 2; COMB Node = 'next_pc[0]~1'
     Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.940 ns; Loc. = LAB_X12_Y12; Fanout = 2; COMB Node = 'next_pc[1]~3'
     Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.011 ns; Loc. = LAB_X12_Y12; Fanout = 2; COMB Node = 'next_pc[2]~5'
     Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.082 ns; Loc. = LAB_X12_Y12; Fanout = 2; COMB Node = 'next_pc[3]~7'
     Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.153 ns; Loc. = LAB_X12_Y12; Fanout = 2; COMB Node = 'next_pc[4]~9'
     Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.224 ns; Loc. = LAB_X12_Y12; Fanout = 2; COMB Node = 'next_pc[5]~11'
     Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.295 ns; Loc. = LAB_X12_Y12; Fanout = 1; COMB Node = 'next_pc[6]~13'
     Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 1.705 ns; Loc. = LAB_X12_Y12; Fanout = 33; COMB Node = 'next_pc[7]~14'
     Info: 10: + IC(0.819 ns) + CELL(0.142 ns) = 2.666 ns; Loc. = M4K_X13_Y11; Fanout = 1; MEM Node = 'rom1:inst_cache|altsyncram:rom_rtl_0|altsyncram_6781:auto_generated|ram_block1a0~porta_address_reg7'
     Info: Total cell delay = 1.392 ns ( 52.21 % )
     Info: Total interconnect delay = 1.274 ns ( 47.79 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
     Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y12 to location X10_Y23
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
     Info: Optimizations that may affect the design's routability were skipped
     Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 72 output pins without output pin load capacitance assignment
     Info: Pin "pc[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "pc[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "pc[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "pc[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "pc[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "pc[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "pc[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "pc[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "ir[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "results[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: Following 32 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
     Info: Pin results[0] has GND driving its datain port
     Info: Pin results[1] has GND driving its datain port
     Info: Pin results[2] has GND driving its datain port
     Info: Pin results[3] has GND driving its datain port
     Info: Pin results[4] has GND driving its datain port
     Info: Pin results[5] has GND driving its datain port
     Info: Pin results[6] has GND driving its datain port
     Info: Pin results[7] has GND driving its datain port
     Info: Pin results[8] has GND driving its datain port
     Info: Pin results[9] has GND driving its datain port
     Info: Pin results[10] has GND driving its datain port
     Info: Pin results[11] has GND driving its datain port
     Info: Pin results[12] has GND driving its datain port
     Info: Pin results[13] has GND driving its datain port
     Info: Pin results[14] has GND driving its datain port
     Info: Pin results[15] has GND driving its datain port
     Info: Pin results[16] has GND driving its datain port
     Info: Pin results[17] has GND driving its datain port
     Info: Pin results[18] has GND driving its datain port
     Info: Pin results[19] has GND driving its datain port
     Info: Pin results[20] has GND driving its datain port
     Info: Pin results[21] has GND driving its datain port
     Info: Pin results[22] has GND driving its datain port
     Info: Pin results[23] has GND driving its datain port
     Info: Pin results[24] has GND driving its datain port
     Info: Pin results[25] has GND driving its datain port
     Info: Pin results[26] has GND driving its datain port
     Info: Pin results[27] has GND driving its datain port
     Info: Pin results[28] has GND driving its datain port
     Info: Pin results[29] has GND driving its datain port
     Info: Pin results[30] has GND driving its datain port
     Info: Pin results[31] has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 5 warnings
     Info: Peak virtual memory: 238 megabytes
     Info: Processing ended: Mon Apr 09 13:43:44 2012
     Info: Elapsed time: 00:00:32
     Info: Total CPU time (on all processors): 00:00:11
Info: *******************************************************************
Info: Running Quartus II Assembler
     Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
     Info: Processing started: Mon Apr 09 13:43:56 2012
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off mrisc1 -c mrisc1
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
     Info: Peak virtual memory: 219 megabytes
     Info: Processing ended: Mon Apr 09 13:44:03 2012
     Info: Elapsed time: 00:00:07
     Info: Total CPU time (on all processors): 00:00:04
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
     Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
     Info: Processing started: Mon Apr 09 13:44:05 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mrisc1 -c mrisc1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
     Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 260.01 MHz between source register "pc[0]~reg0" and destination memory "rom1:inst_cache|altsyncram:rom_rtl_0|altsyncram_6781:auto_generated|ram_block1a18~porta_address_reg7"
     Info: fmax restricted to Clock High delay (1.923 ns) plus Clock Low delay (1.923 ns) : restricted to 3.846 ns. Expand message to see actual delay path.
          Info: + Longest register to memory delay is 3.008 ns
               Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y12_N9; Fanout = 3; REG Node = 'pc[0]~reg0'
               Info: 2: + IC(0.318 ns) + CELL(0.393 ns) = 0.711 ns; Loc. = LCCOMB_X12_Y12_N12; Fanout = 2; COMB Node = 'next_pc[0]~1'
               Info: 3: + IC(0.000 ns) + CELL(0.159 ns) = 0.870 ns; Loc. = LCCOMB_X12_Y12_N14; Fanout = 2; COMB Node = 'next_pc[1]~3'
               Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.941 ns; Loc. = LCCOMB_X12_Y12_N16; Fanout = 2; COMB Node = 'next_pc[2]~5'
               Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.012 ns; Loc. = LCCOMB_X12_Y12_N18; Fanout = 2; COMB Node = 'next_pc[3]~7'
               Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.083 ns; Loc. = LCCOMB_X12_Y12_N20; Fanout = 2; COMB Node = 'next_pc[4]~9'
               Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.154 ns; Loc. = LCCOMB_X12_Y12_N22; Fanout = 2; COMB Node = 'next_pc[5]~11'
               Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.225 ns; Loc. = LCCOMB_X12_Y12_N24; Fanout = 1; COMB Node = 'next_pc[6]~13'
               Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 1.635 ns; Loc. = LCCOMB_X12_Y12_N26; Fanout = 3; COMB Node = 'next_pc[7]~14'
               Info: 10: + IC(1.231 ns) + CELL(0.142 ns) = 3.008 ns; Loc. = M4K_X13_Y12; Fanout = 14; MEM Node = 'rom1:inst_cache|altsyncram:rom_rtl_0|altsyncram_6781:auto_generated|ram_block1a18~porta_address_reg7'
               Info: Total cell delay = 1.459 ns ( 48.50 % )
               Info: Total interconnect delay = 1.549 ns ( 51.50 % )
          Info: - Smallest clock skew is 0.059 ns
               Info: + Shortest clock path from clock "clock" to destination memory is 2.728 ns
                    Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
                    Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 24; COMB Node = 'clock~clkctrl'
                    Info: 3: + IC(0.950 ns) + CELL(0.661 ns) = 2.728 ns; Loc. = M4K_X13_Y12; Fanout = 14; MEM Node = 'rom1:inst_cache|altsyncram:rom_rtl_0|altsyncram_6781:auto_generated|ram_block1a18~porta_address_reg7'
                    Info: Total cell delay = 1.660 ns ( 60.85 % )
                    Info: Total interconnect delay = 1.068 ns ( 39.15 % )
               Info: - Longest clock path from clock "clock" to source register is 2.669 ns
                    Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
                    Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 24; COMB Node = 'clock~clkctrl'
                    Info: 3: + IC(1.015 ns) + CELL(0.537 ns) = 2.669 ns; Loc. = LCFF_X12_Y12_N9; Fanout = 3; REG Node = 'pc[0]~reg0'
                    Info: Total cell delay = 1.536 ns ( 57.55 % )
                    Info: Total interconnect delay = 1.133 ns ( 42.45 % )
          Info: + Micro clock to output delay of source is 0.250 ns
          Info: + Micro setup delay of destination is 0.035 ns
Info: tco from clock "clock" to destination pin "ir[30]" through memory "rom1:inst_cache|altsyncram:rom_rtl_0|altsyncram_6781:auto_generated|ram_block1a18~porta_address_reg0" is 10.331 ns
     Info: + Longest clock path from clock "clock" to source memory is 2.728 ns
          Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
          Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 24; COMB Node = 'clock~clkctrl'
          Info: 3: + IC(0.950 ns) + CELL(0.661 ns) = 2.728 ns; Loc. = M4K_X13_Y12; Fanout = 14; MEM Node = 'rom1:inst_cache|altsyncram:rom_rtl_0|altsyncram_6781:auto_generated|ram_block1a18~porta_address_reg0'
          Info: Total cell delay = 1.660 ns ( 60.85 % )
          Info: Total interconnect delay = 1.068 ns ( 39.15 % )
     Info: + Micro clock to output delay of source is 0.209 ns
     Info: + Longest memory to pin delay is 7.394 ns
          Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y12; Fanout = 14; MEM Node = 'rom1:inst_cache|altsyncram:rom_rtl_0|altsyncram_6781:auto_generated|ram_block1a18~porta_address_reg0'
          Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X13_Y12; Fanout = 1; MEM Node = 'rom1:inst_cache|altsyncram:rom_rtl_0|altsyncram_6781:auto_generated|ram_block1a30'
          Info: 3: + IC(1.769 ns) + CELL(2.632 ns) = 7.394 ns; Loc. = PIN_U9; Fanout = 0; PIN Node = 'ir[30]'
          Info: Total cell delay = 5.625 ns ( 76.08 % )
          Info: Total interconnect delay = 1.769 ns ( 23.92 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 140 megabytes
     Info: Processing ended: Mon Apr 09 13:44:06 2012
     Info: Elapsed time: 00:00:01
     Info: Total CPU time (on all processors): 00:00:01
Info: Quartus II Full Compilation was successful. 0 errors, 93 warnings
