isa1 tests the add/sub and logical-operation instructions.
srisc1.zip setup and read instruction memory
srisc2.zip add register file
srisc3.zip add ALU
isa2 tests the shift and rotate instructions.
srisc4.zip add barrel (logarithmic) shifter
isa3 tests the compare instructions.
srisc5.zip add logic for compare instructions
isa4 tests the branch instructions.
srisc6.zip implements branch instructions. This version is the first with instructions executed in non-sequential order.
isa5 tests the jump instructions.
srisc7.zip implements jump instructions.
isa6 tests the 32-bit load/store instructions.
srisc8.zip implements 32-bit load/store instructions.
isa7 tests the variable-size load/store instructions.
srisc9.zip implements variable-size load/store instructions.
Maintained by John Loomis, last updated 20 October 2008