gates1

// netlist.cpp : Defines the entry point for the console application.
//

#include "stdafx.h"
#include <stdio.h>
#include <stdlib.h>
#include <conio.h>
#include "circuit.h"

void pause();

int _tmain(int argc, _TCHAR* argv[])
{
	wchar_t *filename;
	wchar_t buf[128];
	FILE *in;
	if (argc<2) {
		printf("Enter filename: ");
		_getws_s(buf,127);
		filename = buf;
	}
	else filename = argv[1];
	errno_t nerr = _tfopen_s(&in,filename,_T("r"));
	if (nerr) {
		printf("file: %s not found\n",filename);
		pause();
		return EXIT_FAILURE;
	}
	eCircuit ckt;
	ckt.read(in);
	fclose(in);
	ckt.build_node_list();
	ckt.list_devices();
	printf("\nNode list:\n");
	ckt.list_nodes();
	// test logic simulation
	eNode *A = ckt.find_node("A");
	eNode *B = ckt.find_node("B");
	eNode *out1 = ckt.find_node("out1");
	eNode *out2 = ckt.find_node("out2");
	double v[2] = {0.0, 1.0};
	printf("\n%4s %4s %4s %4s cycles\n","A","B","out1","out2");
	for (int i=0; i<2; i++) {
		for (int j=0; j<2; j++) {
			ckt.reset_nodes();
			A->set(v[i]);
			B->set(v[j]);
			ckt.run();
			printf("%4c %4c %4c %4c %5d\n",
				A->getLogic(),B->getLogic(),out1->getLogic(), out2->getLogic(),ckt.cycles);
		}
	}
	pause();
	return 0;
}

void pause()
{
	printf("Press any key to exit ...\n");
	_getch();
}

Results

This simulation suggests an xnor gate not an xor gate!

 1:  % inverter
 2:  INV g1 A out1
 3:  XOR g2 out2 A B
 4:  
INV g1 nodes 0 1 	value 0  loc[0 0]
XOR g2 nodes 2 0 3 	value 0  loc[0 0]

Node list:
0  A
1  out1
2  out2
3  B

   A    B out1 out2 cycles
   1    1    0    1     1
   1    0    0    0     1
   0    1    1    0     1
   0    0    1    1     1
Press any key to exit ...