# Second Nios II System

Our second Nios II system uses SDRAM instead of the on-chip memory of the Cyclone II FPGA.

The SDRAM chip on the DE2 board has the capacity of 64 Mbits (8 Mbytes). It is organized as 1M x 16 bits x 4 banks.

### Crreate the System

1. Open a new project in Quartus II. Remember to specify a directory NOT on the desktop and with a pathname that does not contain spaces. The name of the project is usually the same as the top-level module. I chose to name my project `sys2`, so my top-level module will be `sys2.v`

2. Use the SOPC Builder to generate the Nios II system. See the instructions below for the SOPC Builder

3. Add PLL for SDRAM Clock. Follow the instructions below for adding the PLL.

4. Write the top-level Verilog module to instantiate the PLL and the Nios II cpu.

   You may download my version of the top-level module from sys2.zip. The module sys2.v uses the DE2 pin names specified in `DE2_pin_assignments.csv`. It connects the 18 toggle switches to `inport` and the 32 output bits to the seven-segment displays, suppresssing leading zeros.

5. Import the DE2 pin assignments and compile the system.

6. Generate a "Hello, World!" C application (not `hello_world_small`) to test the new system.

### Using the SOPC Builder

When you start the SOPC Builder you will be asked for the name of your processor. Do NOT use the name of your top-level project. I chose to name my processor `processor2` in the dialog box shown below.

Figure 1. System Creation dialog

Include the following components as shown in Figure 2. Some of the components require additional explanation.

1. Nios II processor. You might as well use the full-featured version (F)
2. SDRAM Controller (see instructions)
3. Interval timer (accept defaults)
4. JTAG UART (accept defaults)
5. LCD display (rename component to `lcd`)
6. PIO (see instructions)

Exit SOPC Builder to complete the rest of the system. You can generate the CPU now or do it later.

Figure 2. SOPC System Summary

#### Add the SDRAM Controller

To add the SDRAM, select Avalon Components >Memory >SDRAM Controller and click Add. A window depicted in Figure 3 appears. Set the Data Width parameter to 16 bits and leave the default values for the rest. Uncheck the option to Include a functional memory model in the system testbench. Click Finish. Now, in the window of Figure 3, there will be an `sdram_0` module added to the design. Since there is only one SDRAM on the DE2 board, you may rename this module to simply `sdram`, by right-clicking on the original name and selecting rename.

Figure 3. SDRAM Controller

#### Add a PIO unit

Add a PIO unit as shown in Figure 4. Include 32 bits, both input and output ports. Add support for detecting edge transistions and using them to trigger interrupts.

xs

Figure 4. PIO

### Using a Phase-Locked Loop (PLL)

The clock skew depends on physical characteristics of the DE2 board. For proper operation of the SDRAM chip, it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds. This can be accomplished by using a phase-locked loop (PLL) circuit. There exists a Quartus II Megafunction, called ALTPLL, which can be used to generate the desired circuit. The circuit can be created, by using the Quartus II MegaWizard Plug-In Manager, as follows:

1. Select `Tools >MegaWizard Plug-In Manager`. Choose the action Create a new custom megafunction variation and click `Next`.

2. In the window in Figure 5, specify that Cyclone II is the device family used and that the circuit should be defined in Verilog HDL. Also, specify that the generated output (Verilog) file should be called `sdram_pll.v`. From the list of megafunctions in the left box select `I/O >ALTPLL`. Click `Next`.

   Figure 5. ALTPLL Megafunction

3. In Figure 6, specify that the frequency of the inclock0 input is 50 MHz. Leave the other parameters as given by default. Click `Next` to reach the window in Figure 7.

   Figure 6. ALTPLL Wizard page 3

4. We are interested only in the input signal inclock0 and the output signal c0. Remove the other two signals shown in the block diagram in the figure by de-selecting the optional input areset as well as the locked output, as indicated in the figure. Click Next on this page as well as on page 5, until you reach page 6 which is shown in Figure 8.

   Figure 7. ALTPLL Wizard page 5

5. The shifted clock signal is called `c0`. Specify that the output clock frequency is 50 MHz. Also, specify that a phase shift of -3 ns is required, as indicated in the figure. Click `Finish`, which advances to the summary page.

   Figure 8. ALTPLL Wizard page 6

6. In the summary window, click `Finish` to complete the process.

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design sdram_pll.v. The design sdram_pll.v has Cyclone II FAST pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. CLK0 multiply by = 1, CLK0 divide by = 1, CLK0 phase_shift = -3000

Figure 10. Wave showing NORMAL mode operation.

Maintained by John Loomis, last updated 20 June 2007