## `sys2.v`

    module sys2(
      // Clock Input (50 MHz)
      input  CLOCK_50,
      //  Push Buttons
      input  [3:0]  KEY,
      //  DPDT Switches
      input  [17:0]  SW,
      //  7-SEG Displays
      output  [6:0]  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
      //  LEDs
      output  [8:0]  LEDG,  //  LED Green[8:0]
      output  [17:0]  LEDR,  //  LED Red[17:0]
    //    LCD Module 16X2
       inout  [7:0]    LCD_DATA,    //    LCD Data bus 8 bits
       output        LCD_ON,        //    LCD Power ON/OFF
       output        LCD_BLON,    //    LCD Back Light ON/OFF
       output        LCD_RW,        //    LCD Read/Write Select, 0 = Write, 1 = Read
       output        LCD_EN,        //    LCD Enable
       output        LCD_RS,        //    LCD Command/Data Select, 0 = Command, 1 = Data

    //        SDRAM Interface
       inout  [15:0] DRAM_DQ,    //    SDRAM Data bus 16 Bits
       output [11:0] DRAM_ADDR,    //    SDRAM Address bus 12 Bits
       output        DRAM_LDQM,    //    SDRAM Low-byte Data Mask
       output        DRAM_UDQM,    //    SDRAM High-byte Data Mask
       output        DRAM_WE_N,    //    SDRAM Write Enable
       output        DRAM_CAS_N,    //    SDRAM Column Address Strobe
       output        DRAM_RAS_N,    //    SDRAM Row Address Strobe
       output        DRAM_CS_N,    //    SDRAM Chip Select
       output        DRAM_BA_0,    //    SDRAM Bank Address 0
       output        DRAM_BA_1,    //    SDRAM Bank Address 0
       output        DRAM_CLK,    //    SDRAM Clock
       output        DRAM_CKE,    //    SDRAM Clock Enable

      //  GPIO Connections
      inout  [35:0]  GPIO_0, GPIO_1
    );

    //  set all inout ports to tri-state
    assign    DRAM_DQ        =    16'hzzzz;
    assign  GPIO_0    =  36'hzzzzzzzzz;
    assign  GPIO_1    =  36'hzzzzzzzzz;

    wire RST;
    assign RST = KEY[0];

    // Connect dip switches to red LEDS
    assign LEDR[17:0] = SW[17:0];

    //    LCD ON
    assign    LCD_ON        =    1'b1;
    assign    LCD_BLON    =    1'b1;

    wire [31:0] inport, outport;
    assign inport[20:18] = KEY[3:1];
    assign inport[17:0] = SW;
    assign inport[31:21] = 0;
    //assign outport = inport;

    // map to 7-segment displays
    wire [6:0] dig1, dig2, dig3, dig4, dig5, dig6, dig7;
    hex_7seg dsp7(outport[31:28],dig7);
    hex_7seg dsp6(outport[27:24],dig6);
    hex_7seg dsp5(outport[23:20],dig5);
    hex_7seg dsp4(outport[19:16],dig4);
    hex_7seg dsp3(outport[15:12],dig3);
    hex_7seg dsp2(outport[11:8],dig2);
    hex_7seg dsp1(outport[7:4],dig1);
    hex_7seg dsp0(outport[3:0],HEX0);

    // blank leading zeros
    wire [6:0] blank = 7'b111_1111;
    wire [7:0] leading;
    assign leading[7] = (outport[31:28]==4'b0000);
    assign leading[6] = (outport[27:24]==4'b0000) & leading[7];
    assign leading[5] = (outport[23:20]==4'b0000) & leading[6];
    assign leading[4] = (outport[19:16]==4'b0000) & leading[5];
    assign leading[3] = (outport[15:12]==4'b0000) & leading[4];
    assign leading[2] = (outport[11:8]==4'b0000) & leading[3];
    assign leading[1] = (outport[7:4]==4'b0000) & leading[2];
    assign leading[0] = 1'b0;
    assign HEX7 = leading[7]? blank: dig7;
    assign HEX6 = leading[6]? blank: dig6;
    assign HEX5 = leading[5]? blank: dig5;
    assign HEX4 = leading[4]? blank: dig4;
    assign HEX3 = leading[3]? blank: dig3;
    assign HEX2 = leading[2]? blank: dig2;
    assign HEX1 = leading[1]? blank: dig1;

    sdram_pll pll(
        .inclk0(CLOCK_50),
        .c0(DRAM_CLK)
    );

    processor2 our_cpu(
    // 1) global signals:
        .clk(CLOCK_50),
        .reset_n(RST),

    // the_lcd
       .LCD_E_from_the_lcd(LCD_EN),
       .LCD_RS_from_the_lcd(LCD_RS),
       .LCD_RW_from_the_lcd(LCD_RW),
       .LCD_data_to_and_from_the_lcd(LCD_DATA),

     // the_sdram
       .zs_addr_from_the_sdram(DRAM_ADDR),
       .zs_ba_from_the_sdram({DRAM_BA_1,DRAM_BA_0}),
       .zs_cas_n_from_the_sdram(DRAM_CAS_N),
       .zs_cke_from_the_sdram(DRAM_CKE),
       .zs_cs_n_from_the_sdram(DRAM_CS_N),
       .zs_dq_to_and_from_the_sdram(DRAM_DQ),
       .zs_dqm_from_the_sdram({DRAM_UDQM,DRAM_LDQM}),
       .zs_ras_n_from_the_sdram(DRAM_RAS_N),
       .zs_we_n_from_the_sdram(DRAM_WE_N),

    // the_pio_0
       .in_port_to_the_pio_0(inport),
       .out_port_from_the_pio_0(outport)

      );

    //  output  [ 31: 0] out_port_from_the_pio_0;
    //  input   [ 31: 0] in_port_to_the_pio_0;
    endmodule

Maintained by John Loomis, last updated 20 June 2007