ECE 533 Computer Design Assignment 1

Your report should include Verilog log and simulations where required.

  1. Write a structural Verilog module for the following logic operation. Simulate its operation.

  2. Write a behavioral Verilog module for a octal counter (0-7) using an always statement. Show a Quartus simulation of the result.

  3. Write Verilog modules for a D-latch and a D-flip-flop (positive edge triggered). Show a Quartus simulation showing the difference in operation for these devices.

  4. Rewrite the following module to correct the syntax errors.

    module 1st_exam(A,B,C,D,F)
    inputs A, B, C;
    Output D, F;
    and g1(E,B,C);
    not g2(d,E,A);
    OR  g1(F,B,C);

Maintained by John Loomis, last updated 1 Sept 2005