Layout Design Rules

The fundamental parameter in the definition of a set of design rules is the minimum line width.

Typically the minimum line width of a process is set to 2l. For instance, for a 0.6 mm process, l = 0.3 mm.

The minimum line width is the smallest mask dimension that can safely be transferred to the semiconductor material.

The practice of using scalable design rules is conservative and commonly followed for small projects, fast prototyping, and educational use. The design rules are expressed in units of l.

Layer Representation

From a designer's viewpoint, all CMOS designs are based on the following entities:

• Substrates and/or tubs, with p-type for NMOS devices and n-type for PMOS devices.

• Diffusion regions (n⁺ and p⁺), defining the areas where transistors can be formed. These regions are often called the active areas. n⁺ active areas are found in p-tubs, and p⁺ active areas in n-tubs. Diffusions of the inverse type are needed to implement contacts to the tubs (tub-ties) or to the substrate. These are called select regions. p⁺ select areas are found in p-tubs, and n⁺ select areas in n-tubs.

• One or more polysilicon layers (poly), which are used to form the gate electrodes of the transistors (but also serve as interconnects over short distances).

• One or more metal interconnect layers (typically Al).

• Contact layers (vias) to provide interlayer connections.

References

C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980.

MOSIS Scalable CMOS (SCMOS) Design Rules

Maintained by John Loomis, last updated 10 Sep 1999