Microelectronics Assignment 6

Your report should be either a Microsoft Word document or a powerpoint presentation. You must submit your JELIB files and SPICE schematics and other associated files.

Each of you have been assigned a device. See class list for your assignment. Note that PMOS and NMOS transistor sizes (W/L in lambda units) have been specified.

1. Use SPICE to layout and model your device. Generate a symbol for your device. Use SPICE to create a test schematic for your device, using the symbol you have designed. Show a waveform verifying its operation.

2. Draw your device circuit in Electric as a schematic view. Draw your symbol as an icon view.

3. Generate a layout view of your device. Power lines should run horizontally. The centers of the power lines (vdd and ground) should be spaced 80 lambda apart. Wells should occupy no more than half of the space between power rails. Connections to inputs and outputs should be through metal-1. Your design should pass DRC (Design Rule Check), ERC (Electrical Rule Check), and NCC (Network Consistency Check). NCC compares your layout and schematic.

4. Generate spice listings and Verilog listings of your device (using Electric). Generate a documentation view in which you briefly describe your component.

5. Copy the transistor parasitics from Electric to LTSpice and use SPICE to measure the rise/fall times and propagation times as a function of load capacitance.

Maintained by John Loomis, last updated 8 October 2008