Microelectronics Assignment 5

Your report should be a Microsoft Word document or PDF. You must submit your JELIB files and SPICE schematics and other associated files.

1. Work through tutorial 4 (see link below). Your report should include layout figures, schematic figures, and other analysis and diagrams discussed in the tutorial.

   Tutorial 4 – Design, layout, and simulation of a CMOS NAND gate – electric_tutorial_4_video.wmv (42:25)

2. Use SPICE to layout and model a two-input NOR gate. This is your device. Choose transistor parameters in units of λ such that the smallest transistor is W/L = 3λ/2λ. Balance the transistors so that the propagation delay or rise/fall times are approximately equal for low-to-high and high-to-low transistions.

3. Generate a symbol in LTSpice for your device. Use SPICE to create a test schematic for your device, using the symbol you have designed. Show a waveform verifying the propagation and rise/fall times. Show another waveform showing that proper operation of the NOR gate.

4. Draw your device circuit in Electric as a schematic view. Draw your symbol as an icon view.

5. Generate a layout view of your device. Power lines should run horizontally with a width of 8&\lambda;. The centers of the power lines (vdd and ground) should be spaced 80 lambda apart. Wells should occupy no more than half of the space between power rails. Connections to inputs and outputs should be through metal-1. Your design should pass DRC (Design Rule Check), ERC (Electrical Rule Check), and NCC (Network Consistency Check). NCC compares your layout and schematic.

6. Generate spice listings and Verilog listings of your device (using Electric). Generate a documentation view in which you briefly describe your component.

Maintained by John Loomis, last updated 16 October 2010