Microelectronics Assignment 5
Your report should be a Microsoft Word document or PDF.
You must submit your JELIB files and SPICE schematics and other associated files.
- Use Electric to create a layout of the inverter you designed in
exercise 5 of assignment 4. It would be easiest, I think, to modify
tutorial 3 for this purpose. Determine the parasitics for this layout,
and incorporate them into your LTSpice design from assignment 4.
Show a netlist of the new LTSpice schematic.
- Using the geometry of the layout above, derive by hand from its
geometry the parasitics (AD, AS, PD, PS) and compare to the Electric
- Use SPICE to generate the DC transfer curve of the above
inverter. Show the test schematic used to generate this curve. Use the
inverter symbol generated from the previous assignment. Then locate the
switch point and transistion points and generate a bar chart showing
the noise margins. Locate these points on the a drawing of the
- Use SPICE to find the linear dependence of the
rise and fall times vs load capacitance for your inverter. You should
include a plot of the data points you generated, a schematic of the
circuit used to generate the data, and the equations of the fitted
lines for high-to-low and low-to-high transitions.
- Substitute another inverter for the load capacitance in the
previous problem, calculate (using SPICE) the rise and fall times for
the first inverter, and use the results of the previous problem to
determine the input capacitance of the second inverter. Compare the
result to the combined gate capacitance of the two transistors in the
Note. In the above two questions, you can use either rise/tall times
(2.2 τ) or propagation delay (0.69 τ) and solve for R
and Cout from the linear fit.
- Generate a three-inverter chain driven by a pulse voltage
source. Find the average propagation delay as a function of the
inverter number. Calculate the equivalent rise and fall time for the
pulse source to most closely represent the inverter waveform. Generate
a diagram in which you shift the time of the waveforms to allign them
to the pulse source. The midpoint voltages (VDD/2) should
all correspond and the rise and fall time of the pulse source should
approximate the rise and fall of the inverter signals. Document the
schematic of the circuit used in this analysis.
- Generate a 15-inverter ring and show a few periods of
oscillation. Show your schematic. Does it matter where you place the
voltage probe? Find the period (and frequency) of oscillation. Compare
to the calculation of frequency based on propagation time.
You may need to place an initial voltage condition on one of the
inverters to get the system to oscillate.
- Work through tutorial 4 (see link below). Your report should
include layout figures, schematic figures, and other analysis and
diagrams discussed in the tutorial.
4 – Design, layout, and simulation of a CMOS NAND gate – electric_tutorial_4_video.wmv
Maintained by John
Loomis, last updated 24 February 2014