Microelectronics Assignment 4

Your report should be either a Microsoft Word document or a powerpoint presentation. All other computer files associated with the assignment (SPICE, spreadsheets, etc.) should be referenced in the main document. Handwritten material should be submitted directly, not scanned.

  1. The diagram below shows a transistor (poly over n+) with a grid spacing of one l square. Assume a process with l = 0.3 mm. Find the transistor parameters (W, L, AD, PD, AS, PS, NRS, NRD). Assume the drain is the active area on the right.

  2. Analyze the circuit below in Spice. Make the transistors W = 6 l and L = 2 l where l = 0.3 mm. Use the AMI-C5 process and use proper body connections. VDD = 5 v. Show your final layout. Find voltages Va and Vb and the current flowing through the transistors.

  3. Given the parameters in the table below

    VTO zero-bias threshold voltage VT0 0.8 V
    GAMMA body-effect parameter g 0.6
    PHI surface to bulk potential 2|fF| 0.6 V
    CJ0 bottom wall depletion capacitance Cj0 4 10-4 F/m2
    MJ botom wall grading coefficient m 0.43
    PB bottom built-in potential f0 0.74 V

    1. Find the threshold voltage if Vsb = 3V

    2. Convert CJ0 to units of fF/mm2.

    3. Find the bottom capacitance of the source if Vsb = 3V and AS = 50p. Note that the equivalent diode is reversed biased (VD is negative).

  4. Given the following information from an NMOS characteristic curve (VGS = 5 Volts):

    VDS (V) ID (mA)
    2.1 237.85
    4.5 326.76
    5.0 328.76

    You may find the following formula useful:

    1. Find the transconductance k and channel modulation l for the simple (level 1) model that match the measured values in the saturation region of the table above. VT = 0.8 V.

    2. Find the effective resistance of the transistor.

    3. Calculate the current ID at VDS = 4 V for the level 1 model.

  5. Design an inverter with the NMOS transistor sized 5x2 (WxL) and the PMOS transistor sized so that the switch point is close to 2.5 V. Show a diagram of the resulting circuit and a copy of the netlist. This inverter should have ports and power node connections and an external symbol representation - like the example we showed in class.

  6. Use SPICE to generate the DC transfer curve of the above inverter. Show the test schematic used to generate this curve. Use the inverter symbol generated from the previous problem. Then locate the switch point and transistion points and generate a bar chart showing the noise margins. Locate these points on the a drawing of the transfer curve.

Maintained by John Loomis, last updated 16 September 2008