Microelectronics Assignment 4

Your report should be a Microsoft Word document. Supplemental computer files associated with the assignment (SPICE, spreadsheets, etc.) should be referenced in the main document and included in your submission, organized in some appropriate manner.

  1. Use SPICE to model the 5-stage transmission line models from Fig 4.46 (p 214) of Weste and Harris. The goal is to reproduce the plot in Fig 4.46(c).

    Neil H. E. Weste and David Harris, CMOS VLSI Design, A Circuits and Systems Perspective, Third Edition,
    Addison Wesley, 2005. ISBN 0-321-14901-7

  2. Work through tutorial 3 (see link below). Your report should include layout figures, schematic figures, and a report of Spice analysis.

    Tutorial 3 – Design, layout, and simulation of a CMOS inverter – electric_tutorial_3_video.wmv (27:45)

  3. Design an inverter with the NMOS transistor sized 6x2 (WxL), and the PMOS transistor sized so that the switch point is close to 2.5 V. Show a diagram of the resulting circuit and a copy of the netlist. This inverter should have ports and power node connections and an external symbol representation - like the example we showed in class.

  4. Use SPICE to generate the DC transfer curve of the above inverter. Show the test schematic used to generate this curve. Use the inverter symbol generated from the previous problem. Then locate the switch point and transistion points and generate a bar chart showing the noise margins. Locate these points on the a drawing of the transfer curve.

  5. Use SPICE to find the linear dependence of the halfway-point rise and fall delays vs load capacitance for your inverter. You should include a plot of the data points you generated, a schematic of the circuit used to generate the data, and the equations of the fitted lines for high-to-low and low-to-high transitions.

  6. Substitute another inverter for the load capacitance in the previous problem, calculate (using SPICE) the rise and fall times for the first inverter, and use the results of the previous problem to determine the input capacitance of the second inverter. Compare the result to the combined gate capacitance of the two transistors in the inverter.

  7. Generate a three-inverter chain driven by a pulse voltage source. Find the average propagation delay as a function of the inverter number. Calculate the equivalent rise and fall time for the pulse source to most closely represent the inverter waveform. Generate a diagram in which you shift the time of the waveforms to allign them to the pulse source. The midpoint voltages (VDD/2) should all correspond and the rise and fall time of the pulse source should approximate the rise and fall of the inverter signals. Document the schematic of the circuit used in this analysis.

  8. Generate a 15-inverter ring and show a few periods of oscillation. Show your schematic. Does it matter where you place the voltage probe? Find the period (and frequency) of oscillation. Hint: You may need to place an initial voltage condition on one of the inverters to get the system to oscillate.

Maintained by John Loomis, last updated 27 September 2010