Assignment 3

Turn in your assignment on Isidore. Your report should be a Microsoft Word document. Upload all appropriate computer files associated with the assignment, such as SPICE .asc files and Excel spreadsheets.

Download: AMI-C5 technology files

  1. Use spice to generate a set of I-V curves for a NMOS transistor using the CMOSN model in ami_c5.lib. Make the transistor W/L = 2.4µm/0.6µm. Transfer the curves to an excel file and plot the results in excel.

  2. Use spice to generate a set of I-V curves for a PMOS transistor using the CMOSP model in ami_c5.lib. Make the transistor W/L = 8.4µm/1.6µm.

  3. Work through tutorial 2 (see link below). Your report should include a layout figure, schematic figure, and a report of Spice analysis for the transistors.

    Tutorial 2 – Layout and simulating the IV curves of PMOS and NMOS devices – electric_tutorial_2_video.wmv (33:57)

  4. Use spice to find the current and voltage shown for two NMOS transistors in series, shown below (VDD = 5 volts). Include the proper body connections (not shown). Make the transistors W/L = 7/2, meaning W = 2.1 µm and L = 0.6 µm.

  5. The diagram below shows a transistor (poly over n+) with a grid spacing of one λ square. Assume a process with λ = 0.3 µm. Find the transistor parameters (W, L, AD, PD, AS, PS, NRS, NRD). Assume the drain is the active area on the right.

  6. Analyze the circuit below in Spice. Make the transistors W = 6 λ and L = 2 λ where λ = 0.3 µm. Use the AMI-C5 process and use proper body connections. VDD = 5 v. Show your final layout. Find voltages Va and Vb and the current flowing through the transistors.

  7. Given the parameters in the table below

    VTO zero-bias threshold voltage VT0 0.8 V
    GAMMA body-effect parameter γ 0.6
    PHI surface to bulk potential 2|φ| 0.6 V
    CJ0 bottom wall depletion capacitance Cj0 4 10-4 F/m2
    MJ botom wall grading coefficient m 0.43
    PB bottom built-in potential φ0 0.74 V

    1. Find the threshold voltage if Vsb = 3V

    2. Convert CJ0 to units of fF/µm2.

    3. Find the bottom capacitance of the source if Vsb = 3V and AS = 50p. Note that the equivalent diode is reversed biased (VD is negative).

  8. Given the following information from an NMOS characteristic curve (VGS = 5 Volts):

    VDS (V) ID (µA)
    2.1 237.85
    4.5 326.76
    5.0 328.76

    You may find the following formula useful:

    1. Find the transconductance k and channel modulation λ for the simple (level 1) model that match the measured values in the saturation region of the table above. VT = 0.8 V.

    2. Find the effective resistance of the transistor.

    3. Calculate the current ID at VDS = 4 V for the level 1 model.

Maintained by John Loomis, last updated 19 September 2010