RiSC-16 Processor
RiSC-16 computer by Bruce
Jacob, University of Maryland.
- jsim1 (RiSC-16, LW and SW
instructions)
- RiSC16 slides (zip file)
- Download jsim2 skeleton.
This is skeleton of a multi-stage RiSC-16 computer. Lines (or
sections) of code have been removed where indicated by comments.
- jsim3 v1 Non-working version
of pipelined RiSC-16 processor
- jsim3 v2 Three-cycle
pipeline (four-cycle for data read/write). Does not handle branch/jump
instructions.
- jsim3 v3 First working
version of full processor (all instructions).
- risclab1. DE2 implementaion
of pipelined RiSC-16 processor.
pipelining examples
The following are the result of running pipe16nf.exe
and pipe16.exe
RiSC-16 pipeline (single memory)
Winter 2007
Winter 2006
Maintained by John Loomis,
last updated 4 April 2011