RiSC-16 Pipeline CPU – DE2 Project

Download project files.

This is a DE2-hardware version of a pipelined RiSC-16 processor. The stored program is the same as the simulation project jsim3 v3.

The CPU clock can be set to 1 second by setting SW17. Otherwise the clock is 50 MHz. LEDG0 is turned on when the CPU is active.

When the CPU is active, HEX6 shows the CPU state (IFE = 1 or MEM = 2). The other states correspond to CPU inactive and HEX6 is blanked.

When the CPU is active, HEX4 shows the current rd register and HEX3:HEX0 shows the value qd in hex. Note that qd is only written to the register file when the write-enable bit is set (state is IFE) and rd > 0. The sequence of values should be the same as shown in the formatted vector table file (see simulation)

SW3 enables display of the cycle count on HEX3:HEX0 and blanks the register value in HEX4.

When the CPU is not active, SW[2:0] determines the register number in HEX4 and corresponding register contents in HEX3:HEX0.

The pushbutton KEY0 resets the CPU.

Quartus Verilog Documentation

Verilog code and compilation reports

Maintained by John Loomis, last updated 21 April 2010