Download project files.
This is a working version of a pipelined RiSC-16 processor. It uses a common program/data memory. This causes a structural hazard in that the instruction fetch and data access can not occur in the same cycle.
Data hazards do not seem to be a problem because the register file does a read-after-write that is fast enough to foward data to the next instruction.
The following tools have been provided, unmodified from the previous version.s
This is Prof. Jacob's RiSC-16 assembler. It reads a program source file (.s) and generates a hex-encoded memory file suitable for use by Altera Quartus to initialize a memory unit.
a prog2.s prog2.txt
The pipeline simulator reads a memory file and generates an output html file. It shows two simulations, the first a single-cycle sinulation and the second a pipeline simulation. The program handles data hazards and inserts bubbles to avoid control hazards.
pipe16 prog1.txt prog2.pipe.html
The Verilog version is a three-stage pipeline rather than a four-stage pipeline, and uses 1 bubble per branch/jump rather than 2. The Verilog version runs in few cycles than the simulation.
Given the source code (in the src folder), you should be able to modify the program to correspond to the Verilog design.
The specialized Quartus table viewer reads a Quartus Vector Table Output file (.tbl) and generates an html file that captures the state of the system at each positive clock pulse.
jsim3view prog2.sim.tbl view2.html
Maintained by John Loomis, last updated 15 April 2010