JSIM3 – Pipelined RiSC-16 Processor

Download project files.

This is a “not-yet” partially working version of a pipelined RiSC-16 processor. It uses a common program/data memory. This causes a structural hazard in that the instruction fetch and data access can not occur in the same cycle.

This version handles the non-branching instructions. The pipeline was reduced to three stages: instruction fetch, decode and execute, and writeback. Memory access requires an extra clock cycle.

Data hazards do not seem to be a problem because the register file does a read-after-write that is fast enough to foward data to the next instruction.

The following tools have been provided, unmodified from the previous version.

Assembler

This is Prof. Jacob's RiSC-16 assembler. It reads a program source file (.s) and generates a hex-encoded memory file suitable for use by Altera Quartus to initialize a memory unit.

Example usage:

    a prog1.s prog1.txt

Pipeline Simulator

The pipeline simulator reads a memory file and generates an output html file. It shows two simulations, the first a single-cycle sinulation and the second a pipeline simulation. The program handles data hazards and inserts bubbles to avoid control hazards.

Example usage:

   pipe16 prog1.txt prog1.pipe.html

Note that when the output of the pipeline does not match the output of the single-cycle simulation, that entry is highlighted in red.

Altera Quartus Vector Table Output File Viewer

The specialized Quartus table viewer reads a Quartus Vector Table Output file (.tbl) and generates an html file that captures the state of the system at each positive clock pulse.

Example usage:

   jsim3view prog1.sim.tbl view1.html

Quartus Verilog Documentation

Verilog code and compilation reports

Vector Waveform Display


Maintained by John Loomis, last updated 10 April 2010