How to run tests in Project 3
-----------------------------

In project 3, you will have two separate files, called "init.usr" and "init.sys"
where "init.usr" corresponds to the "init.dat" files that you have used before:
it simply contains user code.  If the processor's virtual memory system is 
working correctly, that code can be loaded at *any* location in the physical
memory space, and the software should simply work (provided the page tables
are set up correctly).  The "init.sys" code is the operating system's view of
physical memory -- that portion of physical memory containing the operating 
system's critical components (vector tables, page tables, handlers, etc.).  In
this project, it is a single page: page 0.

For PHASE I, there is no virtual memory system, so init.sys and init.usr are
overlapped ... i.e. they are loaded onto the same physical page in memory, page 0.
To avoid any problems with this, the OS should not put anything valuable down in 
the lower address numbers (e.g., the first 64 words).  This explains the "space 64"
directive at the beginning of "sys-i.s" ... and, in principle, the user code
can be absolutely anything.  In the exampe I give you, the code simply calls the
HALT instruction -- a TRAP to the HALT vector.

You can set up your test-bench this way:

a3 sys-i.s init.sys
a3 usr-i.s init.usr
verilog test-i.v yourcode.v memories.v

For other phases, you will get other .s and .v files.

The main purpose of PHASE II is to test out your TLB.  Thus, the only real change
will be to move the user code (the contents of "init.usr") to a different physical
page, instead of page 0.  The test-ii.v file does this for you, and it also 
initializes your TLB and PSR appropriately so that the ASID is 9, and the TLB 
has a mapping for ASID 9 from virtual page 0 to the physical page that the code 
has been loaded into.  The system image (init.sys) and user code image (init.usr)
don't need to change at all, but I have provided files (sys-ii.s and usr-ii.s) 
nonetheless.
