
Example 1
---------

Here is a very short example program:

	lw	1, 0, data1	# $1= mem[data1]
	halt
data1:	.fill	12345

It assembles to the following machine code:

a402
e071
3039

When we run it on a pipelined simulator we get the following:

memory[0]=a402
memory[1]=e071
memory[2]=3039
3 memory words
	instruction memory:
		instrMem[ 0 ] = lw 1 0 2
		instrMem[ 1 ] = halt
		instrMem[ 2 ] = addi 4 0 57
@@@
state before cycle 0 starts
	pc 0
	data memory:
		dataMem[ 0 ] -23550
		dataMem[ 1 ] -8079
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction: nop
		pc 0
	IDEX:
		instruction: nop
		pc 0
		operand0 0
		operand1 0
		operand2 0
	EXMEM:
		instruction: nop
		pc 0
		storeData 0
		aluResult 0
		branchTarget 0
	MEMWB:
		instruction: nop
		pc 0
		writeData 0
	WBEND:
		instruction: nop
		writeData 0
@@@
state before cycle 1 starts
	pc 1
	data memory:
		dataMem[ 0 ] -23550
		dataMem[ 1 ] -8079
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction: lw 1 0 2
		pc 0
	IDEX:
		instruction: nop
		pc 0
		operand0 0
		operand1 0
		operand2 0
	EXMEM:
		instruction: nop
		pc 0
		storeData 0
		aluResult 0
		branchTarget 0
	MEMWB:
		instruction: nop
		pc 0
		writeData 0
	WBEND:
		instruction: nop
		writeData 0
@@@
state before cycle 2 starts
	pc 2
	data memory:
		dataMem[ 0 ] -23550
		dataMem[ 1 ] -8079
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction: halt
		pc 1
	IDEX:
		instruction: lw 1 0 2
		pc 0
		operand0 2
		operand1 0
		operand2 0
	EXMEM:
		instruction: nop
		pc 0
		storeData 0
		aluResult 0
		branchTarget 0
	MEMWB:
		instruction: nop
		pc 0
		writeData 0
	WBEND:
		instruction: nop
		writeData 0
@@@
state before cycle 3 starts
	pc 3
	data memory:
		dataMem[ 0 ] -23550
		dataMem[ 1 ] -8079
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction: addi 4 0 57
		pc 2
	IDEX:
		instruction: halt
		pc 1
		operand0 -15
		operand1 0
		operand2 0
	EXMEM:
		instruction: lw 1 0 2
		pc 0
		storeData 0
		aluResult 2
		branchTarget 0
	MEMWB:
		instruction: nop
		pc 0
		writeData 0
	WBEND:
		instruction: nop
		writeData 0
@@@
state before cycle 4 starts
	pc 4
	data memory:
		dataMem[ 0 ] -23550
		dataMem[ 1 ] -8079
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 0
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction: nop
		pc 3
	IDEX:
		instruction: addi 4 0 57
		pc 2
		operand0 57
		operand1 0
		operand2 0
	EXMEM:
		instruction: halt
		pc 1
		storeData 0
		aluResult 0
		branchTarget 0
	MEMWB:
		instruction: lw 1 0 2
		pc 0
		writeData 12345
	WBEND:
		instruction: nop
		writeData 0
@@@
state before cycle 5 starts
	pc 5
	data memory:
		dataMem[ 0 ] -23550
		dataMem[ 1 ] -8079
		dataMem[ 2 ] 12345
	registers:
		reg[ 0 ] 0
		reg[ 1 ] 12345
		reg[ 2 ] 0
		reg[ 3 ] 0
		reg[ 4 ] 0
		reg[ 5 ] 0
		reg[ 6 ] 0
		reg[ 7 ] 0
	IFID:
		instruction: nop
		pc 4
	IDEX:
		instruction: nop
		pc 3
		operand0 0
		operand1 0
		operand2 0
	EXMEM:
		instruction: addi 4 0 57
		pc 2
		storeData 0
		aluResult 57
		branchTarget 0
	MEMWB:
		instruction: halt
		pc 1
		writeData 0
	WBEND:
		instruction: lw 1 0 2
		writeData 12345
machine halted
total of 5 cycles executed
