This page is devoted to the 16-bit Ridiculously Simple Computer (RiSC-16), a teaching ISA used by Prof. Bruce L. Jacob at the University of Maryland. The computer is based on the Little Computer (LC-896) developed by Peter Chen at the University of Michigan.
The following notes are extracted from two classes:
| ID | Project Files | |
| Project 1 | p1a.pdf | p1a.zip |
| Project 2 | p2a.pdf | |
| Project 3 | p3a.pdf | p3a.zip |
| Project 4 | p4a.pdf | p4a.zip |
This describes, among other things, the use of adaptive/dynamic state machines (e.g. saturating counters) to track branch behavior and to predict future behavior based on that observed past behavior.
A nice description of the branch-target buffer and a description of what Yeh & Patt call a "static training" branch prediction scheme in which a branch history (string of bits signifying taken/not-taken status of most recent branch outcomes) is used to generate a prediction. That prediction can be generated by profiling a set of benchmarks. The article also explores a few other adaptive state machines besides saturating counters.
By the way, the article is huge, weighing in at 16MB. Here is a 3MB file, with a bit of a image-quality tradeoff (I photocopied it from the original).
Combines the concept of the history-indexed table, as described in Lee & Smith [1984] (called static training by Yeh & Patt) and the use of adaptive state machines, as described in Smith [1981]. Instead of putting a static prediction bit into the table, an adaptive state machine is put into each entry in the table. Note that later papers by Yeh & Patt change the name of the scheme to "two-level adaptive branch prediction" (dropping the "training").
| ID | Write-up | Project files |
| Project 1 | p1b.pdf | p1b.zip |
| Project 2 | p2b.pdf | p2b.zip |
| Synthesis 1 | s1b.pdf | s1examples.v |
| Project 3 | p3b.pdf | p3b.zip |
| File Name | Document Name | Document Description |
| F2002-RiSC-ISA.pdf | The RiSC-16 Instruction-Set Architecture | Describes the instruction-set architecture: machine-code forms, assembly-code forms, etc. |
| F2002-RiSC-seq.pdf | RiSC-16: Sequential Implementation | Describes a sequential implementation of the architecture: control flow, data flow, etc. |
| F2002-RiSC-pipe.pdf | The Pipelined RiSC-16 | Describes a pipelined implementation of the architecture: control flow, data flow, pipeline stages, pipeline hazards, data forwarding, etc. |
Written by Prof. Bruce L. Jacob, Electrical & Computer Engineering, University of Maryland.
Maintained by John Loomis, last updated 15 March 2010