ECE 449 Assignment 6

1. Write an assembly language program to test the RiSC-16 pipeline processor (see jsim3 v3 notes). You will need to change the name of the memory initialization file in the Verilog, recompile the project, simulate the run, save a vector table file, and run jsim3view to show the results. You should compare these to the results of simulation with pipe16. Challenge the processor to make it fail: time-comsuming adds, multiple branch/jumps, multiple memory accesses, read-after-write operations, etc.

2. Modify the code in pipe16.cpp simulate a 3-stage pipeline. The cycle count should match that generated by the Verilog version of the processor.

Maintained by John Loomis, last updated 15 April 2010