RiSC-16 Program 2

Assembled Code and Source

#
# test.s
#
# program to demonstrate RiSC-16 core
# (uses all opcodes)
#

	lw	r1, r0, arg1

	lw	r3, r0, count

	add	r4, r0, r0

loop:	lw	r2, r4, arg2

	movi	r7, sub

	jalr	r7, r7

	addi	r3, r3, -1

	addi	r4, r4, 1

	bne	r3, 0, loop

exit:	sw	r1, r0, diff

	halt

#
# subtract function
#

sub:	nand	r2, r2, r2

	addi	r2, r2, 1

	add	r1, r1, r2

	jalr	r0, r7

#
# data:
#
# count is the number of items to subtract from arg1
# (in this case, 3: arg2 and two beyond it)
# diff is where the result is placed
#

count:	.fill	3

arg1:	.fill	8476

arg2:	.fill	2

	.fill	3

	.fill	4

	.fill	1

	.fill	345

diff:	.fill	0

Simulation Results

#	pc	op	rd	qd	ra	qa
1	00	LW	1	211C	0	0000
2	01	LW	3	0003	0	0000
3	02	ADD	4	0000	0	0000
4	03	LW	2	0002	4	0000
5	04	LUI	7	0000	0	0000
6	05	ADDI	7	000C	7	0000
7	06	JALR	7	0007	7	000c
8	0C	NAND	2	FFFD	2	0002
9	0D	ADDI	2	FFFE	2	fffd
10	0E	ADD	1	211A	1	211c
11	0F	JALR	0	0010	7	0007
12	07	ADDI	3	0002	3	0003
13	08	ADDI	4	0001	4	0000
14	09	BNE	3	0001	0	0000
15	03	LW	2	0003	4	0001
16	04	LUI	7	0000	0	0000
17	05	ADDI	7	000C	7	0000
18	06	JALR	7	0007	7	000c
19	0C	NAND	2	FFFC	2	0003
20	0D	ADDI	2	FFFD	2	fffc
21	0E	ADD	1	2117	1	211a
22	0F	JALR	0	0010	7	0007
23	07	ADDI	3	0001	3	0002
24	08	ADDI	4	0002	4	0001
25	09	BNE	3	0001	0	0000
26	03	LW	2	0004	4	0002
27	04	LUI	7	0000	0	0000
28	05	ADDI	7	000C	7	0000
29	06	JALR	7	0007	7	000c
30	0C	NAND	2	FFFB	2	0004
31	0D	ADDI	2	FFFC	2	fffb
32	0E	ADD	1	2113	1	2117
33	0F	JALR	0	0010	7	0007
34	07	ADDI	3	0000	3	0001
35	08	ADDI	4	0003	4	0002
36	09	BNE	3	0000	0	0000
37	0A	SW	1	2113	0	0000

Registers

format	r1	r2	r3	r4	r5	r6	r7
hex	2113	FFFC	0000	0003	5555	6666	0007
decimal	8467	-4	0	3	21845	26214	7

Memory

addr	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0000	A411	AC10	1000	AA12	7C00	3F8C	FF80	2DFF	3201	CC79	8417	E071	4902	2901	0482	E380
0010	0003	211C	0002	0003	0004	0001	0159	2113