| 1 | Tu | Aug 21 | Introduction to VLSI Design | chap 1 |
| 2 | Th | Aug 23 | Fabrication processes, layers, design rules | chap 3.1, 5.1-5.2 |
| 3 | Tu | Aug 28 | intro to LASI | lab |
| 4 | Th | Aug 30 | passive components (resistors, capacitors) | chap 3.1 |
| 5 | Tu | Sep 4 | active components (p-n diodes, MOSFET transitor) | chap 3.2, 6.1 |
| 6 | Th | Sep 6 | intro to P-Spice | lab |
| 7 | Tu | Sep 11 | MOS transistor I-V characteristics, parasitics | chap 6 |
| 8 | Th | Sep 13 | CMOS Inverter, Layout, Transfer function | chap 5 |
| 9 | Tu | Sep 17 | Inverter, L-Edit layout and Spice simulation | lab |
| 10 | Th | Sep 20 | Inverter delay, power losses, input/output capacitance | chap 7.1-7.3 |
| 11 | Tu | Sep 25 | Test 1 | |
| 12 | Th | Sep 27 | CMOS logic gates, NAND, NOR, AOI | chap 2.1-2.4, 7.4-7.5 |
| 13 | Tu | Oct 2 | Transmission gate, tri-state output | chap 2.5, 7.8 |
| 14 | Th | Oct 4 | combinational logic design in Verilog | lab |
| 15 | Tu | Oct 9 | latches | chap 11.6 |
| Th | Oct 11 | Midterm break | | |
| 16 | Tu | Oct 15 | Flip-flops, registers | chap 11.7-11.8 |
| 17 | Th | Oct 16 | Schmidt trigger, voltage pumps | p 554-556 |
| 18 | Tu | Oct 23 | sequential circuit design | chap 15 |
| 19 | Th | Oct 25 | Test 2 | |
| 20 | Tu | Oct 30 | design lab | lab |
| 21 | Th | Nov 1 | Latch-up, driving large loads, interconnect | chap 8 |
| 22 | Tu | Nov 6 | Lithography video Dynamic gates, clocked logic | chap 4 sect 6.3, chap 10 |
| 23 | Th | Nov 8 | Deposition video | chap 4 |
| 24 | Tu | Nov 12 | Implantation video Memory Circuits, SRAM, sense amplifiers | chap 4 chap 12 |
| 25 | Th | Nov 15 | Etch video Decoders, DRAM, other memory cells | chap 4 chap 12 |
| 26 | Tu | Nov 20 | ESD, I/O Circuits, Packaging | sect 2.3 |
| Th | Nov 22 | Thanksgiving | ||
| 27 | Tu | Nov 27 | Subsystem design | chap 11 |
| 28 | Th | Nov 29 | Design lab | lab |
| 29 | Tu | Dec 4 | Presentations | lab |
| 30 | Mon | Dec 10 | Test 3 (10:10 am - 12 pm) |
Maintained by John Loomis, last updated 20 August 2007