1. Process Family Description
This
non-silicided CMOS process has 3 metal layers and 2 poly
layers, and a high resistance layer. Stacked contacts are
supported. The process is for 5 volt applications. MOSIS
orders epi wafers for this process. For further information,
see the AMIS Mixed
Signal Foundry Services web page.
C5N Process
PiP
(poly2 over poly) capacitors (950 aF/µm²) and the HRP (High
Resistance) option are available on multiproject runs.
C5F Process
The
C5F process offers the above layers of C5N plus Thick_Gate,
N_Minus_Implant (Npblk), and P_Minus_Implant (Ppblk).
2. Design Rules
This process support the following design rules
-
| Design Rules |
Lambda
(micro- meter) |
Feature Size
(micro- meter) |
Available From |
| AMI_C5F/N Rules |
n/a
|
0.60
|
AMIS (See Section
3) |
|
| SCMOS_SUBM |
0.30
|
0.60
|
MOSIS in HTML
|
|
| SCMOS |
0.35
|
0.60
(after sizing) |
MOSIS in HTML
|
|
Review the CMP
and antenna guidelines which apply to both sets of
design rules.
|
MOSIS Technology Codes
See Technology
Codes for AMIS C5F/N Process.
Important note about pads
The bonding pads on designs submitted to these runs
should have metal2 (and via2) under the metal3. If these
guidelines are not followed, metal lifting problems can
occur.
3. AMIS Design Rules, Process Specifications, and
SPICE Parameters
- AMIS has sub-licensed MOSIS to distribute this
information to customers who do not have a MyAMIS account. To
obtain any of these items you must have an account with
MOSIS, submit the on-line AMIS Access Request, then sign
both the Confidentiality Agreement (CDA) and Design Kit
License Agreement (DKLA).
4. Parametric Test Results and SPICE
Model Parameters
See Test
Results for AMIS C5F/N runs.
Related Links
MOSIS-Supported
AMIS Processes
AMIS
Technology Codes & Layer Maps
AMIS
Document Access
|