Assignment 3

Choose (or design) a component with at least four transistors (ECE446) or at least twelve transistors (ECE531).

1. Simulate your component in Spice, and report the results of the simulation. Include your source files in your submission.

2. Simulate your component in Verilog as a transistor model and as gate-level (or behavioral) model. Write a testbench that compares the output of the two models. Include your source files in your submission. Document the results in your report.

3. Make a paper model of the layout.

Paper Model Instructions

1. Use a blank white paper as the substrate. Mark the n-well with a dashed line.

2. Use yellow for p-active, green for n-active, red for polysilicon, light blue for metal 1, and dark blue for metal 2.

3. Paste the active and polysilicon layers to the white paper substrate. Use small black colored squares to locate contacts to the metal areas.

4. Paste the metal 1 layer on your transparent sheet so that it can overlay the lower layers. Mark the contacts on this layer also. They should each align with a lower contact.

5. If you need metal 2, paste it on another transparent sheet to overlay the lower layers. Again mark vias on both the metal 2 and metal 1 layers.

Maintained by John Loomis, last updated 5 Oct 2007