ECE446/ECE531 Microelectronics Assignment 1

  1. Consider the resistance pattern shown below. The line has a width of 1 unit, and the sheet resistance is RS = 22 W. Find the resistance from A to B if each corner square contributes a factor of 5/8 of a "straight-path" square.

  2. An interconnect line (wire) is made from a material that has a resistivity r = 4 mW-cm. The interconnect is 120 mm thick. The line has width of 0.6 mm.
    1. Calculate the sheet resistance RS of the line.
    2. Find the line resistance if the line is 125 mm long.

  3. If the area capacitance of poly2-poly capacitors is 0.94 fF/(mm)2, find the thickness of the SiO2 dielectric layer between the poly and poly2 layers.

  4. Model an RC circuit in Spice where R = 1500 ohms and C = 0.8 pF. Calculate the rise and fall time (from the spice simulation) and relate them to the RC time-constant. Use an ideal square-wave as a signal source. What period did you choose to get valid results?

  5. MOS transistors need high gate capacitance. What materials are proposed or used to increase the dielectric constant over SiO2 = 3.9? Low capacitance is desired between wire layers. What materials are proposed or used to decrease the dieelectric constant of silicon dioxide? Quote the page of textbook (if used), URL of any web documents consulted, or reference any papers.

  6. What is the Copper Damascene process? How does it get its name and why is it used? Identify your sources: textbook, web, or journal.

  7. Describe the technology behind MIM (metal-insulator-metal) and fringe (or fractal) capacitors. Identify your sources.

Maintained by John Loomis, last updated 28 August 2008