Verilog files for final project: srisc.zip.
The following SPICE commands, added to your LTSpice layout, will compute rise and fall times.
.meas TRAN fall TRIG V(out) VAL=4.5 FALL=1 TARG V(out) VAL=0.5 FALL=1
.meas TRAN rise TRIG V(out) VAL=0.5 RISE=1 TARG V(out) VAL=4.5 RISE=1
Change the signal name V(out) as necessary to match your layout. This
will look at the first rise/fall. You can change the RISE and FALL count to look
at later transitions. Output appears in the SPICE Error log (a misleading name since it
contains more than errors). Thank Ken Janulis for working most of this out.
As requested, download directory of LTSPice files. I fixed the problem encountered during class (L and W were backward on the transistors).
Links to SILOS Verilog simulation examples.
Maintained by John Loomis, last updated 20 Aug 2007