Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
     Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
     Info: Processing started: Tue Sep 29 20:53:14 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off reg_file -c reg_file
Info: Found 1 design units, including 1 entities, in source file reg_file.v
     Info: Found entity 1: reg_file
Info: Elaborating entity "reg_file" for the top level hierarchy
Warning: Inferred RAM node "pa~0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Warning: Inferred RAM node "pb~0" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design.
Info: Inferred 2 megafunctions from design logic
     Info: Inferred altsyncram megafunction from the following design logic: "pa~0" 
          Info: Parameter OPERATION_MODE set to DUAL_PORT
          Info: Parameter WIDTH_A set to 32
          Info: Parameter WIDTHAD_A set to 5
          Info: Parameter NUMWORDS_A set to 32
          Info: Parameter WIDTH_B set to 32
          Info: Parameter WIDTHAD_B set to 5
          Info: Parameter NUMWORDS_B set to 32
          Info: Parameter ADDRESS_ACLR_A set to NONE
          Info: Parameter OUTDATA_REG_B set to UNREGISTERED
          Info: Parameter ADDRESS_ACLR_B set to NONE
          Info: Parameter OUTDATA_ACLR_B set to NONE
          Info: Parameter ADDRESS_REG_B set to CLOCK0
          Info: Parameter INDATA_ACLR_A set to NONE
          Info: Parameter WRCONTROL_ACLR_A set to NONE
          Info: Parameter RAM_BLOCK_TYPE set to AUTO
          Info: Parameter INIT_FILE set to db/reg_file.ram0_reg_file_c5668544.hdl.mif
     Info: Inferred altsyncram megafunction from the following design logic: "pb~0" 
          Info: Parameter OPERATION_MODE set to DUAL_PORT
          Info: Parameter WIDTH_A set to 32
          Info: Parameter WIDTHAD_A set to 5
          Info: Parameter NUMWORDS_A set to 32
          Info: Parameter WIDTH_B set to 32
          Info: Parameter WIDTHAD_B set to 5
          Info: Parameter NUMWORDS_B set to 32
          Info: Parameter ADDRESS_ACLR_A set to NONE
          Info: Parameter OUTDATA_REG_B set to UNREGISTERED
          Info: Parameter ADDRESS_ACLR_B set to NONE
          Info: Parameter OUTDATA_ACLR_B set to NONE
          Info: Parameter ADDRESS_REG_B set to CLOCK0
          Info: Parameter INDATA_ACLR_A set to NONE
          Info: Parameter WRCONTROL_ACLR_A set to NONE
          Info: Parameter RAM_BLOCK_TYPE set to AUTO
          Info: Parameter INIT_FILE set to db/reg_file.ram1_reg_file_c5668544.hdl.mif
Info: Elaborated megafunction instantiation "altsyncram:pa_rtl_0"
Info: Instantiated megafunction "altsyncram:pa_rtl_0" with the following parameter:
     Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
     Info: Parameter "WIDTH_A" = "32"
     Info: Parameter "WIDTHAD_A" = "5"
     Info: Parameter "NUMWORDS_A" = "32"
     Info: Parameter "WIDTH_B" = "32"
     Info: Parameter "WIDTHAD_B" = "5"
     Info: Parameter "NUMWORDS_B" = "32"
     Info: Parameter "ADDRESS_ACLR_A" = "NONE"
     Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
     Info: Parameter "ADDRESS_ACLR_B" = "NONE"
     Info: Parameter "OUTDATA_ACLR_B" = "NONE"
     Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
     Info: Parameter "INDATA_ACLR_A" = "NONE"
     Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
     Info: Parameter "RAM_BLOCK_TYPE" = "AUTO"
     Info: Parameter "INIT_FILE" = "db/reg_file.ram0_reg_file_c5668544.hdl.mif"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hvi1.tdf
     Info: Found entity 1: altsyncram_hvi1
Info: Elaborated megafunction instantiation "altsyncram:pb_rtl_1"
Info: Instantiated megafunction "altsyncram:pb_rtl_1" with the following parameter:
     Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
     Info: Parameter "WIDTH_A" = "32"
     Info: Parameter "WIDTHAD_A" = "5"
     Info: Parameter "NUMWORDS_A" = "32"
     Info: Parameter "WIDTH_B" = "32"
     Info: Parameter "WIDTHAD_B" = "5"
     Info: Parameter "NUMWORDS_B" = "32"
     Info: Parameter "ADDRESS_ACLR_A" = "NONE"
     Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
     Info: Parameter "ADDRESS_ACLR_B" = "NONE"
     Info: Parameter "OUTDATA_ACLR_B" = "NONE"
     Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
     Info: Parameter "INDATA_ACLR_A" = "NONE"
     Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
     Info: Parameter "RAM_BLOCK_TYPE" = "AUTO"
     Info: Parameter "INIT_FILE" = "db/reg_file.ram1_reg_file_c5668544.hdl.mif"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ivi1.tdf
     Info: Found entity 1: altsyncram_ivi1
Info: Implemented 297 device resources after synthesis - the final resource count might be different
     Info: Implemented 49 input pins
     Info: Implemented 64 output pins
     Info: Implemented 120 logic cells
     Info: Implemented 64 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
     Info: Peak virtual memory: 177 megabytes
     Info: Processing ended: Tue Sep 29 20:53:25 2009
     Info: Elapsed time: 00:00:11
     Info: Total CPU time (on all processors): 00:00:03
Info: *******************************************************************
Info: Running Quartus II Fitter
     Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
     Info: Processing started: Tue Sep 29 20:53:29 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off reg_file -c reg_file
Info: Selected device EP2C35F672C6 for design "reg_file"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning: Feature LogicLock is not available with your current license
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
     Info: Device EP2C50F672C6 is compatible
     Info: Device EP2C70F672C6 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
     Info: Pin ~ASDO~ is reserved at location E3
     Info: Pin ~nCSO~ is reserved at location D3
     Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: No exact pin location assignment(s) for 113 pins of 113 total pins
     Info: Pin qa[0] not assigned to an exact location on the device
     Info: Pin qa[1] not assigned to an exact location on the device
     Info: Pin qa[2] not assigned to an exact location on the device
     Info: Pin qa[3] not assigned to an exact location on the device
     Info: Pin qa[4] not assigned to an exact location on the device
     Info: Pin qa[5] not assigned to an exact location on the device
     Info: Pin qa[6] not assigned to an exact location on the device
     Info: Pin qa[7] not assigned to an exact location on the device
     Info: Pin qa[8] not assigned to an exact location on the device
     Info: Pin qa[9] not assigned to an exact location on the device
     Info: Pin qa[10] not assigned to an exact location on the device
     Info: Pin qa[11] not assigned to an exact location on the device
     Info: Pin qa[12] not assigned to an exact location on the device
     Info: Pin qa[13] not assigned to an exact location on the device
     Info: Pin qa[14] not assigned to an exact location on the device
     Info: Pin qa[15] not assigned to an exact location on the device
     Info: Pin qa[16] not assigned to an exact location on the device
     Info: Pin qa[17] not assigned to an exact location on the device
     Info: Pin qa[18] not assigned to an exact location on the device
     Info: Pin qa[19] not assigned to an exact location on the device
     Info: Pin qa[20] not assigned to an exact location on the device
     Info: Pin qa[21] not assigned to an exact location on the device
     Info: Pin qa[22] not assigned to an exact location on the device
     Info: Pin qa[23] not assigned to an exact location on the device
     Info: Pin qa[24] not assigned to an exact location on the device
     Info: Pin qa[25] not assigned to an exact location on the device
     Info: Pin qa[26] not assigned to an exact location on the device
     Info: Pin qa[27] not assigned to an exact location on the device
     Info: Pin qa[28] not assigned to an exact location on the device
     Info: Pin qa[29] not assigned to an exact location on the device
     Info: Pin qa[30] not assigned to an exact location on the device
     Info: Pin qa[31] not assigned to an exact location on the device
     Info: Pin qb[0] not assigned to an exact location on the device
     Info: Pin qb[1] not assigned to an exact location on the device
     Info: Pin qb[2] not assigned to an exact location on the device
     Info: Pin qb[3] not assigned to an exact location on the device
     Info: Pin qb[4] not assigned to an exact location on the device
     Info: Pin qb[5] not assigned to an exact location on the device
     Info: Pin qb[6] not assigned to an exact location on the device
     Info: Pin qb[7] not assigned to an exact location on the device
     Info: Pin qb[8] not assigned to an exact location on the device
     Info: Pin qb[9] not assigned to an exact location on the device
     Info: Pin qb[10] not assigned to an exact location on the device
     Info: Pin qb[11] not assigned to an exact location on the device
     Info: Pin qb[12] not assigned to an exact location on the device
     Info: Pin qb[13] not assigned to an exact location on the device
     Info: Pin qb[14] not assigned to an exact location on the device
     Info: Pin qb[15] not assigned to an exact location on the device
     Info: Pin qb[16] not assigned to an exact location on the device
     Info: Pin qb[17] not assigned to an exact location on the device
     Info: Pin qb[18] not assigned to an exact location on the device
     Info: Pin qb[19] not assigned to an exact location on the device
     Info: Pin qb[20] not assigned to an exact location on the device
     Info: Pin qb[21] not assigned to an exact location on the device
     Info: Pin qb[22] not assigned to an exact location on the device
     Info: Pin qb[23] not assigned to an exact location on the device
     Info: Pin qb[24] not assigned to an exact location on the device
     Info: Pin qb[25] not assigned to an exact location on the device
     Info: Pin qb[26] not assigned to an exact location on the device
     Info: Pin qb[27] not assigned to an exact location on the device
     Info: Pin qb[28] not assigned to an exact location on the device
     Info: Pin qb[29] not assigned to an exact location on the device
     Info: Pin qb[30] not assigned to an exact location on the device
     Info: Pin qb[31] not assigned to an exact location on the device
     Info: Pin dc[0] not assigned to an exact location on the device
     Info: Pin clock not assigned to an exact location on the device
     Info: Pin write_enable not assigned to an exact location on the device
     Info: Pin rc[1] not assigned to an exact location on the device
     Info: Pin rc[4] not assigned to an exact location on the device
     Info: Pin rc[0] not assigned to an exact location on the device
     Info: Pin rc[3] not assigned to an exact location on the device
     Info: Pin rc[2] not assigned to an exact location on the device
     Info: Pin ra[0] not assigned to an exact location on the device
     Info: Pin ra[1] not assigned to an exact location on the device
     Info: Pin ra[2] not assigned to an exact location on the device
     Info: Pin ra[3] not assigned to an exact location on the device
     Info: Pin ra[4] not assigned to an exact location on the device
     Info: Pin dc[1] not assigned to an exact location on the device
     Info: Pin dc[2] not assigned to an exact location on the device
     Info: Pin dc[3] not assigned to an exact location on the device
     Info: Pin dc[4] not assigned to an exact location on the device
     Info: Pin dc[5] not assigned to an exact location on the device
     Info: Pin dc[6] not assigned to an exact location on the device
     Info: Pin dc[7] not assigned to an exact location on the device
     Info: Pin dc[8] not assigned to an exact location on the device
     Info: Pin dc[9] not assigned to an exact location on the device
     Info: Pin dc[10] not assigned to an exact location on the device
     Info: Pin dc[11] not assigned to an exact location on the device
     Info: Pin dc[12] not assigned to an exact location on the device
     Info: Pin dc[13] not assigned to an exact location on the device
     Info: Pin dc[14] not assigned to an exact location on the device
     Info: Pin dc[15] not assigned to an exact location on the device
     Info: Pin dc[16] not assigned to an exact location on the device
     Info: Pin dc[17] not assigned to an exact location on the device
     Info: Pin dc[18] not assigned to an exact location on the device
     Info: Pin dc[19] not assigned to an exact location on the device
     Info: Pin dc[20] not assigned to an exact location on the device
     Info: Pin dc[21] not assigned to an exact location on the device
     Info: Pin dc[22] not assigned to an exact location on the device
     Info: Pin dc[23] not assigned to an exact location on the device
     Info: Pin dc[24] not assigned to an exact location on the device
     Info: Pin dc[25] not assigned to an exact location on the device
     Info: Pin dc[26] not assigned to an exact location on the device
     Info: Pin dc[27] not assigned to an exact location on the device
     Info: Pin dc[28] not assigned to an exact location on the device
     Info: Pin dc[29] not assigned to an exact location on the device
     Info: Pin dc[30] not assigned to an exact location on the device
     Info: Pin dc[31] not assigned to an exact location on the device
     Info: Pin rb[0] not assigned to an exact location on the device
     Info: Pin rb[1] not assigned to an exact location on the device
     Info: Pin rb[2] not assigned to an exact location on the device
     Info: Pin rb[3] not assigned to an exact location on the device
     Info: Pin rb[4] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Automatically promoted node clock (placed in PIN P2 (CLK2, LVDSCLK1p, Input))
     Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Starting register packing
Info: Finished register packing
     Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
     Info: Number of I/O pins in group: 112 (unused VREF, 3.3V VCCIO, 48 input, 64 output, 0 bidirectional)
          Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
     Info: Statistics of I/O banks
          Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  63 pins available
          Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  57 pins available
          Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  56 pins available
          Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  58 pins available
          Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  65 pins available
          Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  58 pins available
          Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  58 pins available
          Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  56 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:02
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is memory to memory delay of 2.645 ns
     Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y20; Fanout = 1; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~porta_datain_reg0'
     Info: 2: + IC(0.000 ns) + CELL(2.645 ns) = 2.645 ns; Loc. = M4K_X13_Y20; Fanout = 0; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~porta_memory_reg0'
     Info: Total cell delay = 2.645 ns ( 100.00 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
     Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X11_Y12 to location X21_Y23
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
     Info: Optimizations that may affect the design's routability were skipped
     Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 64 output pins without output pin load capacitance assignment
     Info: Pin "qa[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qa[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
     Info: Pin "qb[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 4 warnings
     Info: Peak virtual memory: 236 megabytes
     Info: Processing ended: Tue Sep 29 20:53:49 2009
     Info: Elapsed time: 00:00:20
     Info: Total CPU time (on all processors): 00:00:12
Info: *******************************************************************
Info: Running Quartus II Assembler
     Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
     Info: Processing started: Tue Sep 29 20:53:56 2009
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off reg_file -c reg_file
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: The Active Serial/Parallel mode CONF_DONE pin error check is disabled
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
     Info: Peak virtual memory: 216 megabytes
     Info: Processing ended: Tue Sep 29 20:54:03 2009
     Info: Elapsed time: 00:00:07
     Info: Total CPU time (on all processors): 00:00:04
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
     Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
     Info: Processing started: Tue Sep 29 20:54:05 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off reg_file -c reg_file --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
     Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 235.07 MHz between source memory "altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~porta_datain_reg0" and destination memory "altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~porta_memory_reg0"
     Info: fmax restricted to Clock High delay (2.127 ns) plus Clock Low delay (2.127 ns) : restricted to 4.254 ns. Expand message to see actual delay path.
          Info: + Longest memory to memory delay is 2.645 ns
               Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y20; Fanout = 1; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~porta_datain_reg0'
               Info: 2: + IC(0.000 ns) + CELL(2.645 ns) = 2.645 ns; Loc. = M4K_X13_Y20; Fanout = 0; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~porta_memory_reg0'
               Info: Total cell delay = 2.645 ns ( 100.00 % )
          Info: - Smallest clock skew is -0.025 ns
               Info: + Shortest clock path from clock "clock" to destination memory is 2.716 ns
                    Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
                    Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 198; COMB Node = 'clock~clkctrl'
                    Info: 3: + IC(0.964 ns) + CELL(0.635 ns) = 2.716 ns; Loc. = M4K_X13_Y20; Fanout = 0; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~porta_memory_reg0'
                    Info: Total cell delay = 1.634 ns ( 60.16 % )
                    Info: Total interconnect delay = 1.082 ns ( 39.84 % )
               Info: - Longest clock path from clock "clock" to source memory is 2.741 ns
                    Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
                    Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 198; COMB Node = 'clock~clkctrl'
                    Info: 3: + IC(0.964 ns) + CELL(0.660 ns) = 2.741 ns; Loc. = M4K_X13_Y20; Fanout = 1; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~porta_datain_reg0'
                    Info: Total cell delay = 1.659 ns ( 60.53 % )
                    Info: Total interconnect delay = 1.082 ns ( 39.47 % )
          Info: + Micro clock to output delay of source is 0.209 ns
          Info: + Micro setup delay of destination is 0.035 ns
Info: tsu for memory "altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_we_reg" (data pin = "rc[0]", clock pin = "clock") is 6.507 ns
     Info: + Longest pin to memory delay is 9.211 ns
          Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_W11; Fanout = 4; PIN Node = 'rc[0]'
          Info: 2: + IC(6.113 ns) + CELL(0.149 ns) = 7.112 ns; Loc. = LCCOMB_X15_Y20_N22; Fanout = 1; COMB Node = 'always1~1'
          Info: 3: + IC(0.261 ns) + CELL(0.420 ns) = 7.793 ns; Loc. = LCCOMB_X15_Y20_N16; Fanout = 3; COMB Node = 'always1~2'
          Info: 4: + IC(1.109 ns) + CELL(0.309 ns) = 9.211 ns; Loc. = M4K_X13_Y21; Fanout = 0; MEM Node = 'altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_we_reg'
          Info: Total cell delay = 1.728 ns ( 18.76 % )
          Info: Total interconnect delay = 7.483 ns ( 81.24 % )
     Info: + Micro setup delay of destination is 0.035 ns
     Info: - Shortest clock path from clock "clock" to destination memory is 2.739 ns
          Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
          Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 198; COMB Node = 'clock~clkctrl'
          Info: 3: + IC(0.961 ns) + CELL(0.661 ns) = 2.739 ns; Loc. = M4K_X13_Y21; Fanout = 0; MEM Node = 'altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_we_reg'
          Info: Total cell delay = 1.660 ns ( 60.61 % )
          Info: Total interconnect delay = 1.079 ns ( 39.39 % )
Info: tco from clock "clock" to destination pin "qa[16]" through memory "altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~portb_address_reg0" is 13.003 ns
     Info: + Longest clock path from clock "clock" to source memory is 2.770 ns
          Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
          Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 198; COMB Node = 'clock~clkctrl'
          Info: 3: + IC(0.964 ns) + CELL(0.689 ns) = 2.770 ns; Loc. = M4K_X13_Y20; Fanout = 32; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~portb_address_reg0'
          Info: Total cell delay = 1.688 ns ( 60.94 % )
          Info: Total interconnect delay = 1.082 ns ( 39.06 % )
     Info: + Micro clock to output delay of source is 0.209 ns
     Info: + Longest memory to pin delay is 10.024 ns
          Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y20; Fanout = 32; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a0~portb_address_reg0'
          Info: 2: + IC(0.000 ns) + CELL(2.991 ns) = 2.991 ns; Loc. = M4K_X13_Y20; Fanout = 1; MEM Node = 'altsyncram:pa_rtl_0|altsyncram_hvi1:auto_generated|ram_block1a16'
          Info: 3: + IC(0.993 ns) + CELL(0.438 ns) = 4.422 ns; Loc. = LCCOMB_X14_Y21_N28; Fanout = 1; COMB Node = 'pa~20'
          Info: 4: + IC(2.804 ns) + CELL(2.798 ns) = 10.024 ns; Loc. = PIN_AF10; Fanout = 0; PIN Node = 'qa[16]'
          Info: Total cell delay = 6.227 ns ( 62.12 % )
          Info: Total interconnect delay = 3.797 ns ( 37.88 % )
Info: th for memory "altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_datain_reg14" (data pin = "dc[14]", clock pin = "clock") is -3.226 ns
     Info: + Longest clock path from clock "clock" to destination memory is 2.738 ns
          Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clock'
          Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 198; COMB Node = 'clock~clkctrl'
          Info: 3: + IC(0.961 ns) + CELL(0.660 ns) = 2.738 ns; Loc. = M4K_X13_Y21; Fanout = 1; MEM Node = 'altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_datain_reg14'
          Info: Total cell delay = 1.659 ns ( 60.59 % )
          Info: Total interconnect delay = 1.079 ns ( 39.41 % )
     Info: + Micro hold delay of destination is 0.234 ns
     Info: - Shortest pin to memory delay is 6.198 ns
          Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_L3; Fanout = 3; PIN Node = 'dc[14]'
          Info: 2: + IC(5.230 ns) + CELL(0.106 ns) = 6.198 ns; Loc. = M4K_X13_Y21; Fanout = 1; MEM Node = 'altsyncram:pb_rtl_1|altsyncram_ivi1:auto_generated|ram_block1a0~porta_datain_reg14'
          Info: Total cell delay = 0.968 ns ( 15.62 % )
          Info: Total interconnect delay = 5.230 ns ( 84.38 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 138 megabytes
     Info: Processing ended: Tue Sep 29 20:54:08 2009
     Info: Elapsed time: 00:00:03
     Info: Total CPU time (on all processors): 00:00:01
Info: Quartus II Full Compilation was successful. 0 errors, 7 warnings
