fifotest.v
// TOP MODULE
module fifotest(
// INPUTS
input reset_n, // Active low reset
input [`FIFO_WIDTH-1:0] data_in, // Data input to FIFO
input read_n, // Read FIFO (active low)
input write_n, // Write FIFO (active low)
// OUTPUTS
output [`FIFO_WIDTH-1:0] data_out, // FIFO data output
output full, // FIFO is full
output empty, // FIFO is empty
output half, // FIFO is half full
// or more
output [`FIFO_BITS-1:0] counter,
output underflow, overflow
);
afifo u(
// INPUTS
.reset_n(reset_n), // Active low reset
.data_in(data_in), // Data input to FIFO
.read_n(read_n), // Read FIFO (active low)
.write_n(write_n), // Write FIFO (active low)
// OUTPUTS
.data_out(data_out), // FIFO data output
.full(full), // FIFO is full
.empty(empty), // FIFO is empty
.half(half), // FIFO is half full or more
.count(counter),
.underflow(underflow),
.overflow(overflow)
);
endmodule
afifo.v
/*********************************************************/
// MODULE: Synchronizing FIFO
//
// FILE NAME: afifo.v
// AUTHOR: Bob Zeidman, Zeidman Consulting
//
//
// DESCRIPTION: This module defines a Synchronizing FIFO.
// The FIFO memory is implemented as a ring buffer. The read
// pointer points to the beginning of the buffer, while the
// write pointer points to the end of the buffer.
//
/*********************************************************/
// DEFINES
`define FIFO_DEPTH 5 // Depth of FIFO (number of bytes)
`define FIFO_HALF 3 // Half depth of FIFO
// (this avoids rounding errors)
`define FIFO_BITS 4 // Number of bits required to
// represent the FIFO size
`define FIFO_WIDTH 8 // Width of FIFO data
// TOP MODULE
module afifo(
// INPUTS
input reset_n, // Active low reset
input [`FIFO_WIDTH-1:0] data_in, // Data input to FIFO
input read_n, // Read FIFO (active low)
input write_n, // Write FIFO (active low)
// OUTPUTS
output reg [`FIFO_WIDTH-1:0] data_out, // FIFO data output
output full, // FIFO is full
output empty, // FIFO is empty
output half, // FIFO is half full
// or more
output [`FIFO_BITS-1:0] count, // How many locations in the FIFO
// are occupied?
output reg underflow, overflow
);
// The FIFO memory.
reg [`FIFO_WIDTH-1:0] fifo_mem[0:`FIFO_DEPTH];
// FIFO read pointer points to
// the location in the FIFO to
// read from next
reg [`FIFO_BITS-1:0] rd_pointer;
// FIFO write pointer points to
// the location in the FIFO to
// write to next
reg [`FIFO_BITS-1:0] wr_pointer;
reg flag;
// PARAMETERS
// ASSIGN STATEMENTS
assign count = (wr_pointer >= rd_pointer?
wr_pointer - rd_pointer:
`FIFO_DEPTH + wr_pointer - rd_pointer);
assign full = (count == `FIFO_DEPTH) ? 1'b1 : 1'b0;
assign empty = (count == 0) ? 1'b1 : 1'b0;
assign half = (count >= `FIFO_HALF) ? 1'b1 : 1'b0;
// MAIN CODE
// Look at the falling edge of the read signal
always @(negedge read_n or negedge reset_n) begin
if (~reset_n) begin
// Reset the FIFO pointer
rd_pointer = `FIFO_BITS'b0;
underflow = 1'b0;
end // Check for FIFO underflow
else if (empty)
underflow = 1'b1;
else
begin
underflow = 1'b0;
// Output the data
data_out <= fifo_mem[rd_pointer];
// Increment the read pointer
// Check if the read pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (rd_pointer == `FIFO_DEPTH)
rd_pointer <= `FIFO_BITS'b0;
else
rd_pointer <= rd_pointer + 1'b1;
end
end
// Look at the falling edge of the write signal
always @(negedge write_n or negedge reset_n) begin
if (~reset_n) begin
// Reset the FIFO pointer
wr_pointer = `FIFO_BITS'b0;
overflow = 1'b0;
end
// Check for FIFO overflow
else if (full)
overflow = 1'b1;
else
begin
overflow = 1'b0;
// Store the data
fifo_mem[wr_pointer] <= data_in;
// Increment the write pointer
// Check if the write pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (wr_pointer == `FIFO_DEPTH)
wr_pointer <= `FIFO_BITS'b0;
else
wr_pointer <= wr_pointer + 1'b1;
end
end
endmodule
fit.summary
Fitter Status : Successful - Tue Oct 20 00:56:52 2009
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : fifotest
Top-level Entity Name : fifotest
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 91 / 33,216 ( < 1 % )
Total combinational functions : 67 / 33,216 ( < 1 % )
Dedicated logic registers : 66 / 33,216 ( < 1 % )
Total registers : 66
Total pins : 28 / 475 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )
tan.summary-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tsu Slack : N/A Required Time : None Actual Time : 4.639 ns From : data_in[4] To : afifo:u|fifo_mem~4 From Clock : -- To Clock : write_n Failed Paths : 0 Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 12.331 ns From : afifo:u|rd_pointer[1] To : empty From Clock : read_n To Clock : -- Failed Paths : 0 Type : Worst-case th Slack : N/A Required Time : None Actual Time : -1.384 ns From : reset_n To : afifo:u|data_out[7] From Clock : -- To Clock : read_n Failed Paths : 0 Type : Clock Setup: 'write_n' Slack : N/A Required Time : None Actual Time : 168.86 MHz ( period = 5.922 ns ) From : afifo:u|wr_pointer[0] To : afifo:u|fifo_mem~39 From Clock : write_n To Clock : write_n Failed Paths : 0 Type : Clock Setup: 'read_n' Slack : N/A Required Time : None Actual Time : 172.62 MHz ( period = 5.793 ns ) From : afifo:u|rd_pointer[1] To : afifo:u|data_out[4] From Clock : read_n To Clock : read_n Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Tue Oct 20 21:32:23 2009