Assignment 2

1. Do part (d) of exercises 2.1, 2.3 and 2.4.

2. Write and verify a Verilog module to generate the boolean function from the previous exercise.

3. Do exercise 2.24.

4. Write and verify a Verilog module that implements the previous exercise for the Cyclone II chip in the DE-2 board. Use your simulation results to determine the maximum propagation delay for output P and output D.

Your Quartus II simulation should group the input bits as shown below:

Maintained by John Loomis, last updated 1 Sept 2008