diglab1.v
module diglab1( // Clock Input (50 MHz) input CLOCK_50, // Push Buttons input [3:0] KEY, // DPDT Switches input [17:0] SW, // 7-SEG Displays output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, // LEDs output [8:0] LEDG, // LED Green[8:0] output [17:0] LEDR, // LED Red[17:0] // GPIO Connections inout [35:0] GPIO_0, GPIO_1 ); // set all inout ports to tri-state assign GPIO_0 = 36'hzzzzzzzzz; assign GPIO_1 = 36'hzzzzzzzzz; // Connect dip switches to red LEDs assign LEDR[17:0] = SW[17:0]; // turn off green LEDs assign LEDG[8:0] = 0; wire [15:0] A; // map to 7-segment displays hex_7seg dsp0(A[3:0],HEX0); hex_7seg dsp1(A[7:4],HEX1); hex_7seg dsp2(A[11:8],HEX2); hex_7seg dsp3(A[15:12],HEX3); wire [6:0] blank = ~7'h00; // blank remaining digits assign HEX4 = blank; assign HEX5 = blank; assign HEX6 = blank; //assign HEX7 = blank; assign HEX7 = ~SW[6:0]; // control (set) value of A, signal with KEY3 //always @(negedge KEY[3]) // A <= SW[15:0]; assign A = SW[15:0]; endmodule
hex_7seg.v
module hex_7seg(hex_digit,seg); input [3:0] hex_digit; output [6:0] seg; reg [6:0] seg; // seg = {g,f,e,d,c,b,a}; // 0 is on and 1 is off always @ (hex_digit) case (hex_digit) 4'h0: seg = ~7'h3F; 4'h1: seg = ~7'h06; // ---a---- 4'h2: seg = ~7'h5B; // | | 4'h3: seg = ~7'h4F; // f b 4'h4: seg = ~7'h66; // | | 4'h5: seg = ~7'h6D; // ---g---- 4'h6: seg = ~7'h7D; // | | 4'h7: seg = ~7'h07; // e c 4'h8: seg = ~7'h7F; // | | 4'h9: seg = ~7'h67; // ---d---- 4'ha: seg = ~7'h77; 4'hb: seg = ~7'h7C; 4'hc: seg = ~7'h39; 4'hd: seg = ~7'h5E; 4'he: seg = ~7'h79; 4'hf: seg = ~7'h71; endcase endmodule
fit.summary
Fitter Status : Successful - Mon Sep 01 23:27:04 2008 Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition Revision Name : diglab1 Top-level Entity Name : diglab1 Family : Cyclone II Device : EP2C35F672C6 Timing Models : Final Total logic elements : 28 / 33,216 ( < 1 % ) Total combinational functions : 28 / 33,216 ( < 1 % ) Dedicated logic registers : 0 / 33,216 ( 0 % ) Total registers : 0 Total pins : 178 / 475 ( 37 % ) Total virtual pins : 0 Total memory bits : 0 / 483,840 ( 0 % ) Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tpd Slack : N/A Required Time : None Actual Time : 10.805 ns From : SW[14] To : HEX3[6] From Clock : -- To Clock : -- Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Mon Sep 01 23:28:24 2008