Audio CODEC

Download: project files

References

The chip system clock is programmed for 384 f_s = 18.434 MHz with a sampling frequency f_s = 48 kHz. The bit clock must run at 32 f_s, and the LR clock at f_s, one channel is available at the rising edge and the other at the falling edge. The bit clock runs at 1/12 of the system clock.

• Stereo phono jack connections.
• ADC sensitivity test
• Coarse study of frequency response
• Comparison of ADC output and DAC output
• Audio waveforms

Maintained by John Loomis, last updated 11 January 2008