Download LTspice files from spice_clocked_inverter.zip.
Download Verilog files from latch.zip.
Download Verilog project files from memtest.zip
SW[17] (left-most) controls enable signal. SW[0] (right-most) controls D signal.
Download Verilog project files from memtlab1.zip
Download Verilog project files from register.zip.
Download Verilog project files from ramtest.zip.
SW[17] (left-most) controls clock: switch on for manual control (using KEY[3]), switch off to use 1 sec clock. KEY[3] is reset switch. The seven-segment displays read the following values (in hex)
7-seg | display |
---|---|
HEX7:6 | addr
|
HEX5:4 | q
|
HEX3:2 | qa
|
HEX1:0 | inst
|
Download Verilog project files from memtlab2.zip
Maintained by John Loomis, last updated 3 Nov 2011