module signed_compare; wire w1, w2; parameter WIDTH = 4; reg signed [WIDTH-1:0] A, B; assign w1 = (A<B); integer nA, nB, N, halfN; initial begin N = 2**WIDTH; halfN = N/2; $display("N = %d\n",N); $display("time A B w1"); for (nA=-halfN ; nA<halfN; nA=nA+1) begin for (nB=-halfN ; nB<halfN; nB=nB+1) begin A<=nA; B<=nB; #1; end end end initial $monitor("%0d %d %d %b",$time,A,B,w1); endmodule