Project: bcdlab

Contents

Verilog Files

bcdlab.v
DE2_Default.v
div10.v
hex_7seg.v

Quartus Files

fit.summary
tan.summary

Verilog Files

bcdlab.v

module bcdlab(
  // Clock Input (50 MHz)
  input  CLOCK_50,
  //  Push Buttons
  input  [3:0]  KEY,
  //  DPDT Switches 
  input  [17:0]  SW,
  //  7-SEG Displays
  output  [6:0]  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
  //  LEDs
  output  [8:0]  LEDG,  //  LED Green[8:0]
  output  [17:0]  LEDR //  LED Red[17:0]
);

// Connect dip switches to red LEDs
assign LEDR[17:0] = SW[17:0];

// turn off green LEDs
assign LEDG[8:0] = 0;

// binary to BCD
wire [19:0] BCD;
div10 u1(SW[15:0],BCD);

// map to 7-segment displays

hex_7seg dsp0(BCD[3:0],HEX0);
hex_7seg dsp1(BCD[7:4],HEX1);
hex_7seg dsp2(BCD[11:8],HEX2);
hex_7seg dsp3(BCD[15:12],HEX3);
hex_7seg dsp4(BCD[19:16],HEX4);

localparam blank = ~7'h00; 

// blank remaining digits
assign HEX5 = blank;
assign HEX6 = blank;
assign HEX7 = blank;

endmodule

DE2_Default.v

// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
//
// Major Functions:    DE2 Default Bitstream
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V1.0 :| Johnny Chen       :| 05/08/19  :|      Initial Revision
//   V1.1 :| Sean Peng         :| 05/09/30  :|      Changed CLOCK, SW, LEDG/R
//                                                  according to Zvonko's requests.
//   V1.2 :| Johnny Chen       :| 05/11/16  :|      Add to FLASH Address FL_ADDR[21:20]
//   V1.3 :| Johnny Chen       :| 05/12/12  :|      Fixed VGA_Audio_PLL Initial Sequence.
//   V1.4 :| Johnny Chen       :| 06/07/12  :|      Modify I2C_AV_Config LUT Data.
// --------------------------------------------------------------------


module DE2_Default (
//    Clock Input
  CLOCK_27,    //    27 MHz
  CLOCK_50,    //    50 MHz
  EXT_CLOCK,    //    External Clock
        ////////////////////    Push Button        ////////////////////
        KEY,                            //    Pushbutton[3:0]
        ////////////////////    DPDT Switch        ////////////////////
        SW,                                //    Toggle Switch[17:0]
        ////////////////////    7-SEG Dispaly    ////////////////////
        HEX0,                            //    Seven Segment Digit 0
        HEX1,                            //    Seven Segment Digit 1
        HEX2,                            //    Seven Segment Digit 2
        HEX3,                            //    Seven Segment Digit 3
        HEX4,                            //    Seven Segment Digit 4
        HEX5,                            //    Seven Segment Digit 5
        HEX6,                            //    Seven Segment Digit 6
        HEX7,                            //    Seven Segment Digit 7
        ////////////////////////    LED        ////////////////////////
        LEDG,                            //    LED Green[8:0]
        LEDR,                            //    LED Red[17:0]
        ////////////////////////    UART    ////////////////////////
        UART_TXD,                        //    UART Transmitter
        UART_RXD,                        //    UART Receiver
        ////////////////////////    IRDA    ////////////////////////
        IRDA_TXD,                        //    IRDA Transmitter
        IRDA_RXD,                        //    IRDA Receiver
        /////////////////////    SDRAM Interface        ////////////////
        DRAM_DQ,                        //    SDRAM Data bus 16 Bits
        DRAM_ADDR,                        //    SDRAM Address bus 12 Bits
        DRAM_LDQM,                        //    SDRAM Low-byte Data Mask 
        DRAM_UDQM,                        //    SDRAM High-byte Data Mask
        DRAM_WE_N,                        //    SDRAM Write Enable
        DRAM_CAS_N,                        //    SDRAM Column Address Strobe
        DRAM_RAS_N,                        //    SDRAM Row Address Strobe
        DRAM_CS_N,                        //    SDRAM Chip Select
        DRAM_BA_0,                        //    SDRAM Bank Address 0
        DRAM_BA_1,                        //    SDRAM Bank Address 0
        DRAM_CLK,                        //    SDRAM Clock
        DRAM_CKE,                        //    SDRAM Clock Enable
        ////////////////////    Flash Interface        ////////////////
        FL_DQ,                            //    FLASH Data bus 8 Bits
        FL_ADDR,                        //    FLASH Address bus 22 Bits
        FL_WE_N,                        //    FLASH Write Enable
        FL_RST_N,                        //    FLASH Reset
        FL_OE_N,                        //    FLASH Output Enable
        FL_CE_N,                        //    FLASH Chip Enable
        ////////////////////    SRAM Interface        ////////////////
        SRAM_DQ,                        //    SRAM Data bus 16 Bits
        SRAM_ADDR,                        //    SRAM Address bus 18 Bits
        SRAM_UB_N,                        //    SRAM High-byte Data Mask 
        SRAM_LB_N,                        //    SRAM Low-byte Data Mask 
        SRAM_WE_N,                        //    SRAM Write Enable
        SRAM_CE_N,                        //    SRAM Chip Enable
        SRAM_OE_N,                        //    SRAM Output Enable
        ////////////////////    ISP1362 Interface    ////////////////
        OTG_DATA,                        //    ISP1362 Data bus 16 Bits
        OTG_ADDR,                        //    ISP1362 Address 2 Bits
        OTG_CS_N,                        //    ISP1362 Chip Select
        OTG_RD_N,                        //    ISP1362 Write
        OTG_WR_N,                        //    ISP1362 Read
        OTG_RST_N,                        //    ISP1362 Reset
        OTG_FSPEED,                        //    USB Full Speed,    0 = Enable, Z = Disable
        OTG_LSPEED,                        //    USB Low Speed,     0 = Enable, Z = Disable
        OTG_INT0,                        //    ISP1362 Interrupt 0
        OTG_INT1,                        //    ISP1362 Interrupt 1
        OTG_DREQ0,                        //    ISP1362 DMA Request 0
        OTG_DREQ1,                        //    ISP1362 DMA Request 1
        OTG_DACK0_N,                    //    ISP1362 DMA Acknowledge 0
        OTG_DACK1_N,                    //    ISP1362 DMA Acknowledge 1
        ////////////////////    LCD Module 16X2        ////////////////
        LCD_ON,                            //    LCD Power ON/OFF
        LCD_BLON,                        //    LCD Back Light ON/OFF
        LCD_RW,                            //    LCD Read/Write Select, 0 = Write, 1 = Read
        LCD_EN,                            //    LCD Enable
        LCD_RS,                            //    LCD Command/Data Select, 0 = Command, 1 = Data
        LCD_DATA,                        //    LCD Data bus 8 bits
        ////////////////////    SD_Card Interface    ////////////////
        SD_DAT,                            //    SD Card Data
        SD_DAT3,                        //    SD Card Data 3
        SD_CMD,                            //    SD Card Command Signal
        SD_CLK,                            //    SD Card Clock
        ////////////////////    USB JTAG link    ////////////////////
        TDI,                              // CPLD -> FPGA (data in)
        TCK,                              // CPLD -> FPGA (clk)
        TCS,                              // CPLD -> FPGA (CS)
        TDO,                              // FPGA -> CPLD (data out)
        ////////////////////    I2C        ////////////////////////////
        I2C_SDAT,                        //    I2C Data
        I2C_SCLK,                        //    I2C Clock
        ////////////////////    PS2        ////////////////////////////
        PS2_DAT,                        //    PS2 Data
        PS2_CLK,                        //    PS2 Clock
        ////////////////////    VGA        ////////////////////////////
        VGA_CLK,                           //    VGA Clock
        VGA_HS,                            //    VGA H_SYNC
        VGA_VS,                            //    VGA V_SYNC
        VGA_BLANK,                        //    VGA BLANK
        VGA_SYNC,                        //    VGA SYNC
        VGA_R,                           //    VGA Red[9:0]
        VGA_G,                             //    VGA Green[9:0]
        VGA_B,                          //    VGA Blue[9:0]
        ////////////    Ethernet Interface    ////////////////////////
        ENET_DATA,                        //    DM9000A DATA bus 16Bits
        ENET_CMD,                        //    DM9000A Command/Data Select, 0 = Command, 1 = Data
        ENET_CS_N,                        //    DM9000A Chip Select
        ENET_WR_N,                        //    DM9000A Write
        ENET_RD_N,                        //    DM9000A Read
        ENET_RST_N,                        //    DM9000A Reset
        ENET_INT,                        //    DM9000A Interrupt
        ENET_CLK,                        //    DM9000A Clock 25 MHz
        ////////////////    Audio CODEC        ////////////////////////
        AUD_ADCLRCK,                    //    Audio CODEC ADC LR Clock
        AUD_ADCDAT,                        //    Audio CODEC ADC Data
        AUD_DACLRCK,                    //    Audio CODEC DAC LR Clock
        AUD_DACDAT,                        //    Audio CODEC DAC Data
        AUD_BCLK,                        //    Audio CODEC Bit-Stream Clock
        AUD_XCK,                        //    Audio CODEC Chip Clock
        ////////////////    TV Decoder        ////////////////////////
        TD_DATA,                        //    TV Decoder Data bus 8 bits
        TD_HS,                            //    TV Decoder H_SYNC
        TD_VS,                            //    TV Decoder V_SYNC
        TD_RESET,                        //    TV Decoder Reset
        ////////////////////    GPIO    ////////////////////////////
        GPIO_0,                            //    GPIO Connection 0
        GPIO_1                            //    GPIO Connection 1
    );

////////////////////////    Clock Input         ////////////////////////
input            CLOCK_27;                //    27 MHz
input            CLOCK_50;                //    50 MHz
input            EXT_CLOCK;                //    External Clock
////////////////////////    Push Button        ////////////////////////
input    [3:0]    KEY;                    //    Pushbutton[3:0]
////////////////////////    DPDT Switch        ////////////////////////
input    [17:0]    SW;                        //    Toggle Switch[17:0]
////////////////////////    7-SEG Dispaly    ////////////////////////
output    [6:0]    HEX0;                    //    Seven Segment Digit 0
output    [6:0]    HEX1;                    //    Seven Segment Digit 1
output    [6:0]    HEX2;                    //    Seven Segment Digit 2
output    [6:0]    HEX3;                    //    Seven Segment Digit 3
output    [6:0]    HEX4;                    //    Seven Segment Digit 4
output    [6:0]    HEX5;                    //    Seven Segment Digit 5
output    [6:0]    HEX6;                    //    Seven Segment Digit 6
output    [6:0]    HEX7;                    //    Seven Segment Digit 7
////////////////////////////    LED        ////////////////////////////
output    [8:0]    LEDG;                    //    LED Green[8:0]
output    [17:0]    LEDR;                    //    LED Red[17:0]
////////////////////////////    UART    ////////////////////////////
output            UART_TXD;                //    UART Transmitter
input            UART_RXD;                //    UART Receiver
////////////////////////////    IRDA    ////////////////////////////
output            IRDA_TXD;                //    IRDA Transmitter
input            IRDA_RXD;                //    IRDA Receiver
///////////////////////        SDRAM Interface    ////////////////////////
inout    [15:0]    DRAM_DQ;                //    SDRAM Data bus 16 Bits
output    [11:0]    DRAM_ADDR;                //    SDRAM Address bus 12 Bits
output            DRAM_LDQM;                //    SDRAM Low-byte Data Mask 
output            DRAM_UDQM;                //    SDRAM High-byte Data Mask
output            DRAM_WE_N;                //    SDRAM Write Enable
output            DRAM_CAS_N;                //    SDRAM Column Address Strobe
output            DRAM_RAS_N;                //    SDRAM Row Address Strobe
output            DRAM_CS_N;                //    SDRAM Chip Select
output            DRAM_BA_0;                //    SDRAM Bank Address 0
output            DRAM_BA_1;                //    SDRAM Bank Address 0
output            DRAM_CLK;                //    SDRAM Clock
output            DRAM_CKE;                //    SDRAM Clock Enable
////////////////////////    Flash Interface    ////////////////////////
inout    [7:0]    FL_DQ;                    //    FLASH Data bus 8 Bits
output    [21:0]    FL_ADDR;                //    FLASH Address bus 22 Bits
output            FL_WE_N;                //    FLASH Write Enable
output            FL_RST_N;                //    FLASH Reset
output            FL_OE_N;                //    FLASH Output Enable
output            FL_CE_N;                //    FLASH Chip Enable
////////////////////////    SRAM Interface    ////////////////////////
inout    [15:0]    SRAM_DQ;                //    SRAM Data bus 16 Bits
output    [17:0]    SRAM_ADDR;                //    SRAM Address bus 18 Bits
output            SRAM_UB_N;                //    SRAM High-byte Data Mask
output            SRAM_LB_N;                //    SRAM Low-byte Data Mask 
output            SRAM_WE_N;                //    SRAM Write Enable
output            SRAM_CE_N;                //    SRAM Chip Enable
output            SRAM_OE_N;                //    SRAM Output Enable
////////////////////    ISP1362 Interface    ////////////////////////
inout    [15:0]    OTG_DATA;                //    ISP1362 Data bus 16 Bits
output    [1:0]    OTG_ADDR;                //    ISP1362 Address 2 Bits
output            OTG_CS_N;                //    ISP1362 Chip Select
output            OTG_RD_N;                //    ISP1362 Write
output            OTG_WR_N;                //    ISP1362 Read
output            OTG_RST_N;                //    ISP1362 Reset
output            OTG_FSPEED;                //    USB Full Speed,    0 = Enable, Z = Disable
output            OTG_LSPEED;                //    USB Low Speed,     0 = Enable, Z = Disable
input            OTG_INT0;                //    ISP1362 Interrupt 0
input            OTG_INT1;                //    ISP1362 Interrupt 1
input            OTG_DREQ0;                //    ISP1362 DMA Request 0
input            OTG_DREQ1;                //    ISP1362 DMA Request 1
output            OTG_DACK0_N;            //    ISP1362 DMA Acknowledge 0
output            OTG_DACK1_N;            //    ISP1362 DMA Acknowledge 1
////////////////////    LCD Module 16X2    ////////////////////////////
inout    [7:0]    LCD_DATA;                //    LCD Data bus 8 bits
output            LCD_ON;                    //    LCD Power ON/OFF
output            LCD_BLON;                //    LCD Back Light ON/OFF
output            LCD_RW;                    //    LCD Read/Write Select, 0 = Write, 1 = Read
output            LCD_EN;                    //    LCD Enable
output            LCD_RS;                    //    LCD Command/Data Select, 0 = Command, 1 = Data
////////////////////    SD Card Interface    ////////////////////////
inout            SD_DAT;                    //    SD Card Data
inout            SD_DAT3;                //    SD Card Data 3
inout            SD_CMD;                    //    SD Card Command Signal
output            SD_CLK;                    //    SD Card Clock
////////////////////////    I2C        ////////////////////////////////
inout            I2C_SDAT;                //    I2C Data
output            I2C_SCLK;                //    I2C Clock
////////////////////////    PS2        ////////////////////////////////
input             PS2_DAT;                //    PS2 Data
input            PS2_CLK;                //    PS2 Clock
////////////////////    USB JTAG link    ////////////////////////////
input              TDI;                    // CPLD -> FPGA (data in)
input              TCK;                    // CPLD -> FPGA (clk)
input              TCS;                    // CPLD -> FPGA (CS)
output             TDO;                    // FPGA -> CPLD (data out)
////////////////////////    VGA            ////////////////////////////
output            VGA_CLK;                   //    VGA Clock
output            VGA_HS;                    //    VGA H_SYNC
output            VGA_VS;                    //    VGA V_SYNC
output            VGA_BLANK;                //    VGA BLANK
output            VGA_SYNC;                //    VGA SYNC
output    [9:0]    VGA_R;                   //    VGA Red[9:0]
output    [9:0]    VGA_G;                     //    VGA Green[9:0]
output    [9:0]    VGA_B;                   //    VGA Blue[9:0]
////////////////    Ethernet Interface    ////////////////////////////
inout    [15:0]    ENET_DATA;                //    DM9000A DATA bus 16Bits
output            ENET_CMD;                //    DM9000A Command/Data Select, 0 = Command, 1 = Data
output            ENET_CS_N;                //    DM9000A Chip Select
output            ENET_WR_N;                //    DM9000A Write
output            ENET_RD_N;                //    DM9000A Read
output            ENET_RST_N;                //    DM9000A Reset
input            ENET_INT;                //    DM9000A Interrupt
output            ENET_CLK;                //    DM9000A Clock 25 MHz
////////////////////    Audio CODEC        ////////////////////////////
output/*inout*/    AUD_ADCLRCK;            //    Audio CODEC ADC LR Clock
input            AUD_ADCDAT;                //    Audio CODEC ADC Data
inout            AUD_DACLRCK;            //    Audio CODEC DAC LR Clock
output            AUD_DACDAT;                //    Audio CODEC DAC Data
inout            AUD_BCLK;                //    Audio CODEC Bit-Stream Clock
output            AUD_XCK;                //    Audio CODEC Chip Clock
////////////////////    TV Devoder        ////////////////////////////
input    [7:0]    TD_DATA;                //    TV Decoder Data bus 8 bits
input            TD_HS;                    //    TV Decoder H_SYNC
input            TD_VS;                    //    TV Decoder V_SYNC
output            TD_RESET;                //    TV Decoder Reset

//    GPIO
inout    [35:0]    GPIO_0;     //    GPIO Connection 0
inout    [35:0]    GPIO_1;     //    GPIO Connection 1

//    LCD ON
assign    LCD_ON        =    1'b1;
assign    LCD_BLON    =    1'b1;

//    All inout port turn to tri-state
assign    DRAM_DQ        =    16'hzzzz;
assign    FL_DQ        =    8'hzz;
assign    SRAM_DQ        =    16'hzzzz;
assign    OTG_DATA    =    16'hzzzz;
assign    SD_DAT        =    1'bz;
assign    ENET_DATA    =    16'hzzzz;
assign    GPIO_0        =    36'hzzzzzzzzz;
assign    GPIO_1        =    36'hzzzzzzzzz;

wire [31:0]    mSEG7_DIG;
reg     [31:0]    Cont;
wire        VGA_CTRL_CLK;
wire        AUD_CTRL_CLK;
wire [9:0]    mVGA_R;
wire [9:0]    mVGA_G;
wire [9:0]    mVGA_B;
wire [19:0]    mVGA_ADDR;
wire        DLY_RST;

always@(posedge CLOCK_50 or negedge KEY[0])
begin
    if(!KEY[0])
    Cont    <=    0;
    else
    Cont    <=    Cont+1;
end

assign    TD_RESET    =    1'b1;    //    Bypress 27 MHz
assign    AUD_ADCLRCK    =    AUD_DACLRCK;
assign    AUD_XCK        =    AUD_CTRL_CLK;
assign    mSEG7_DIG    =    {    Cont[27:24],Cont[27:24],Cont[27:24],Cont[27:24],
                            Cont[27:24],Cont[27:24],Cont[27:24],Cont[27:24]    };
assign    LEDR        =    {    Cont[25:23],Cont[25:23],Cont[25:23],
                            Cont[25:23],Cont[25:23],Cont[25:23]    };
assign    LEDG        =    {    Cont[25:23],Cont[25:23],Cont[25:23]    };

Reset_Delay            r0    (    .iCLK(CLOCK_50),.oRESET(DLY_RST)    );

VGA_Audio_PLL         p1    (    .areset(~DLY_RST),.inclk0(CLOCK_27),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(VGA_CLK)    );

SEG7_LUT_8             u0    (    HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,mSEG7_DIG );

VGA_Controller        u1    (    //    Host Side
                            .iCursor_RGB_EN(4'h7),
                            .oAddress(mVGA_ADDR),
                            .iRed(mVGA_R),
                            .iGreen(mVGA_G),
                            .iBlue(mVGA_B),
                            //    VGA Side
                            .oVGA_R(VGA_R),
                            .oVGA_G(VGA_G),
                            .oVGA_B(VGA_B),
                            .oVGA_H_SYNC(VGA_HS),
                            .oVGA_V_SYNC(VGA_VS),
                            .oVGA_SYNC(VGA_SYNC),
                            .oVGA_BLANK(VGA_BLANK),
                            //    Control Signal
                            .iCLK(VGA_CTRL_CLK),
                            .iRST_N(DLY_RST)    );

VGA_OSD_RAM            u2    (    //    Read Out Side
                            .oRed(mVGA_R),
                            .oGreen(mVGA_G),
                            .oBlue(mVGA_B),
                            .iVGA_ADDR(mVGA_ADDR),
                            .iVGA_CLK(VGA_CLK),
                            //    CLUT
                            .iON_R(1023),
                            .iON_G(1023),
                            .iON_B(1023),
                            .iOFF_R(0),
                            .iOFF_G(0),
                            .iOFF_B(512),
                            //    Control Signals
                            .iRST_N(DLY_RST)    );

I2C_AV_Config         u3    (    //    Host Side
                            .iCLK(CLOCK_50),
                            .iRST_N(KEY[0]),
                            //    I2C Side
                            .I2C_SCLK(I2C_SCLK),
                            .I2C_SDAT(I2C_SDAT)    );

AUDIO_DAC             u4    (    //    Audio Side
                            .oAUD_BCK(AUD_BCLK),
                            .oAUD_DATA(AUD_DACDAT),
                            .oAUD_LRCK(AUD_DACLRCK),
                            //    Control Signals
                            .iSrc_Select(SW[17]),
                            .iCLK_18_4(AUD_CTRL_CLK),
                            .iRST_N(DLY_RST)    );

LCD_TEST             u5    (    //    Host Side
                            .iCLK(CLOCK_50),
                            .iRST_N(DLY_RST),
                            //    LCD Side
                            .LCD_DATA(LCD_DATA),
                            .LCD_RW(LCD_RW),
                            .LCD_EN(LCD_EN),
                            .LCD_RS(LCD_RS)    );

endmodule

div10.v

module div10(input [15:0] num, output [19:0] bcd);

wire [15:0] s1, s2, s3, s4;
wire [3:0] ten = 4'd10;
ip_divide u1(.denom(ten),.numer(num),.quotient(s1),.remain(bcd[3:0]));
ip_divide u2(.denom(ten),.numer(s1),.quotient(s2),.remain(bcd[7:4]));
ip_divide u3(.denom(ten),.numer(s2),.quotient(s3),.remain(bcd[11:8]));
ip_divide u4(.denom(ten),.numer(s3),.quotient(s4),.remain(bcd[15:12]));
assign bcd[19:16] = s4[3:0];
endmodule

hex_7seg.v

module hex_7seg(
input [3:0] hex_digit,
output reg [6:0] seg
);
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
        4'h0: seg = ~7'h3F;
        4'h1: seg = ~7'h06;     // ---a----
        4'h2: seg = ~7'h5B;     // |      |
        4'h3: seg = ~7'h4F;     // f      b
        4'h4: seg = ~7'h66;     // |      |
        4'h5: seg = ~7'h6D;     // ---g----
        4'h6: seg = ~7'h7D;     // |      |
        4'h7: seg = ~7'h07;     // e      c
        4'h8: seg = ~7'h7F;     // |      |
        4'h9: seg = ~7'h67;     // ---d----
        4'ha: seg = ~7'h77;
        4'hb: seg = ~7'h7C;
        4'hc: seg = ~7'h39;
        4'hd: seg = ~7'h5E;
        4'he: seg = ~7'h79;
        4'hf: seg = ~7'h71;
endcase

endmodule

Quartus Compilation Summary

fit.summary

Fitter Status : Successful - Tue Oct 18 19:24:11 2011
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : bcdlab
Top-level Entity Name : bcdlab
Family : Cyclone II
Device : EP2C35F672C6
Timing Models : Final
Total logic elements : 237 / 33,216 ( < 1 % )
    Total combinational functions : 237 / 33,216 ( < 1 % )
    Dedicated logic registers : 0 / 33,216 ( 0 % )
Total registers : 0
Total pins : 106 / 475 ( 22 % )
Total virtual pins : 0
Total memory bits : 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

tan.summary

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 34.924 ns
From           : SW[14]
To             : HEX4[6]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------


Maintained by John Loomis, last updated Tue Oct 18 19:24:48 2011