Node:SPARC Options, Next:ARM Options, Previous:VAX Options, Up:Submodel Options
-m options are supported on the SPARC:
-mapp-regsto generate output using the global registers 2 through 4, which the SPARC SVR4 ABI reserves for applications. This is the default.
To be fully SVR4 ABI compliant at the cost of some performance loss,
-mno-app-regs. You should compile libraries and system
software with this option.
sparclite-*-*do provide software floating point support.
-msoft-float changes the calling convention in the output file;
therefore, it is only useful if you compile all of a program with
this option. In particular, you need to compile
library that comes with GCC, with
-msoft-float in order for
this to work.
As of this writing, there are no SPARC implementations that have hardware
support for the quad-word floating point instructions. They all invoke
a trap handler for one of these instructions, and then the trap handler
emulates the effect of the instruction. Because of the trap handler overhead,
this is much slower than calling the ABI library routines. Thus the
-msoft-quad-float option is the default.
-mflat, the compiler does not generate save/restore instructions and will use a "flat" or single register window calling convention. This model uses %i7 as the frame pointer and is compatible with the normal register window model. Code from either may be intermixed. The local registers and the input registers (0-5) are still treated as "call saved" registers and will be saved on the stack as necessary.
-mno-flat (the default), the compiler emits save/restore
instructions (except for leaf functions) and is the normal mode of operation.
These options are deprecated and will be deleted in a future GCC release.
-munaligned-doubles, GCC assumes that doubles have 8 byte
alignment only if they are contained in another type, or if they have an
absolute address. Otherwise, it assumes they have 4 byte alignment.
Specifying this option avoids some rare compatibility problems with code
generated by other compilers. It is not the default because it results
in a performance loss, especially for floating point code.
-mfaster-structs, the compiler assumes that structures should have 8 byte alignment. This enables the use of pairs of
stdinstructions for copies in structure assignment, in place of twice as many
stpairs. However, the use of this changed alignment directly violates the SPARC ABI. Thus, it's intended only for use on targets where the developer acknowledges that their resulting code will not be directly in line with the rules of the ABI.
-mimpure-text, used in addition to
-shared, tells the compiler to not pass
-z textto the linker when linking a shared object. Using this option, you can link position-dependent code into a shared object.
-mimpure-text suppresses the "relocations remain against
allocatable but non-writable sections" linker error message.
However, the necessary relocations will trigger copy-on-write, and the
shared object is not actually shared across processes. Instead of
-mimpure-text, you should compile all source code with
This option is only available on SunOS and Solaris.
Default instruction scheduling parameters are used for values that select
an architecture and not an implementation. These are
Here is a list of each supported architecture and their supported
v7: cypress v8: supersparc, hypersparc sparclite: f930, f934, sparclite86x sparclet: tsc701 v9: ultrasparc, ultrasparc3
By default (unless configured otherwise), GCC generates code for the V7
variant of the SPARC architecture. With
-mcpu=cypress, the compiler
additionally optimizes it for the Cypress CY7C602 chip, as used in the
SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
SPARCStation 1, 2, IPX etc.
-mcpu=v8, GCC generates code for the V8 variant of the SPARC
architecture. The only difference from V7 code is that the compiler emits
the integer multiply and integer divide instructions which exist in SPARC-V8
but not in SPARC-V7. With
-mcpu=supersparc, the compiler additionally
optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
-mcpu=sparclite, GCC generates code for the SPARClite variant of
the SPARC architecture. This adds the integer multiply, integer divide step
and scan (
ffs) instructions which exist in SPARClite but not in SPARC-V7.
-mcpu=f930, the compiler additionally optimizes it for the
Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With
-mcpu=f934, the compiler additionally optimizes it for the Fujitsu
MB86934 chip, which is the more recent SPARClite with FPU.
-mcpu=sparclet, GCC generates code for the SPARClet variant of
the SPARC architecture. This adds the integer multiply, multiply/accumulate,
integer divide step and scan (
ffs) instructions which exist in SPARClet
but not in SPARC-V7. With
-mcpu=tsc701, the compiler additionally
optimizes it for the TEMIC SPARClet chip.
-mcpu=v9, GCC generates code for the V9 variant of the SPARC
architecture. This adds 64-bit integer and floating-point move instructions,
3 additional floating-point condition code registers and conditional move
-mcpu=ultrasparc, the compiler additionally
optimizes it for the Sun UltraSPARC I/II chips. With
-mcpu=ultrasparc3, the compiler additionally optimizes it for the
Sun UltraSPARC III chip.
The same values for
-mcpu=cpu_type can be used for
-mtune=cpu_type, but the only useful values are those
that select a particular cpu implementation. Those are
-mv8plus, GCC generates code for the SPARC-V8+ ABI. The difference from the V8 ABI is that the global and out registers are considered 64-bit wide. This is enabled by default on Solaris in 32-bit mode for all SPARC-V9 processors.
-mvis, GCC generates code that takes advantage of the UltraSPARC Visual Instruction Set extensions. The default is
-m options are supported in addition to the above
on SPARC-V9 processors in 64-bit environments:
-mstack-bias, GCC assumes that the stack pointer, and frame pointer if present, are offset by -2047 which must be added back when making stack frame references. This is the default in 64-bit mode. Otherwise, assume no such offset is present.