Figure 1.
The DE2 board includes a 16-pin D-SUB connector for VGA output. The VGA synchronization signals are provided directly from the Cyclone II FPGA, and the Analog Devices ADV7123 triple 10-bit high-speed video DAC is used to produce the analog data signals (red, green, and blue). The associated schematic is given in Figure 1. Although the DAC can support resolutions of up to 1600 x 1200 pixels (100 Hz refresh), the DE2 board is limited by its system clock to 640 x 480 VGA resolution (60 Hz refresh).
Figure 1.
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on various educational web sites (for example, search for “VGA signal timing”). Figure 2 illustrates the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An active-low pulse of specific duration (time a in the figure) is applied to the horizontal synchronization (hsync) input of the monitor, which signifies the end of one row of data and the start of the next. The data (RGB) inputs on the monitor must be off (driven to 0 V) for a time period called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c). During the data display interval the RGB data drives each pixel in turn across the row being displayed. Finally, there is a time period called the front porch (d) where the RGB signals must again be off before the next hsync pulse can occur. The timing of the vertical synchronization (vsync) is the same as shown in Figure 2, except that a vsync pulse signifies the end of one frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing). Tables 1 and 2 show, for different resolutions, the durations of time periods a, b, c, and d for both horizontal and vertical timing.
Figure 2.
Detailed information for using the ADV7123 video DAC is available in its datasheet. The pin assignments between the Cyclone II FPGA and the ADV7123 are listed in Table 3. An example of code that drives a VGA display is described in Sections 5.2 and 5.3.
Table 2. VGA horizontal timing specification.
| VGA mode | Resolution (HxV) | a(ms) | b(us) | c(us) | d(us) | Pixel clock(Mhz) |
|---|---|---|---|---|---|---|
| VGA(60Hz) | 640x480 | 3.8 | 1.9 | 25.4 | 0.6 | 25 (640/c) |
| VGA(85Hz) | 640x480 | 1.6 | 2.2 | 17.8 | 1.6 | 36 (640/c) |
| SVGA(60Hz) | 800x600 | 3.2 | 2.2 | 20 | 1 | 40 (800/c) |
| SVGA(75Hz) | 800x600 | 1.6 | 3.2 | 16.2 | 0.3 | 49 (800/c) |
| SVGA(85Hz) | 800x600 | 1.1 | 2.7 | 14.2 | 0.6 | 56 (800/c) |
| XGA(60Hz) | 1024x768 | 2.1 | 2.5 | 15.8 | 0.4 | 65 (1024/c) |
| XGA(70Hz) | 1024x768 | 1.8 | 1.9 | 13.7 | 0.3 | 75 (1024/c) |
| XGA(85Hz) | 1024x768 | 1.0 | 2.2 | 10.8 | 0.5 | 95 (1024/c) |
| 1280x1024(60Hz) | 1280x1024 | 1.0 | 2.3 | 11.9 | 0.4 | 108 (1280/c) |
Table 2. VGA vertical timing specification.
| VGA mode | Resolution (HxV) | a(lines) | b(lines) | c(lines) | d(lines) |
|---|---|---|---|---|---|
| VGA(60Hz) | 640x480 | 2 | 33 | 480 | 10 |
| VGA(85Hz) | 640x480 | 3 | 25 | 480 | 1 |
| SVGA(60Hz) | 800x600 | 4 | 23 | 600 | 1 |
| SVGA(75Hz) | 800x600 | 3 | 21 | 600 | 1 |
| SVGA(85Hz) | 800x600 | 3 | 27 | 600 | 1 |
| XGA(60Hz) | 1024x768 | 6 | 29 | 768 | 3 |
| XGA(70Hz) | 1024x768 | 6 | 29 | 768 | 3 |
| XGA(85Hz) | 1024x768 | 3 | 36 | 768 | 1 |
| 1280x1024(60Hz) | 1280x1024 | 3 | 38 | 1024 | 1 |
Table 3. ADV7123 signal assignments.
| Signal Name | Description |
|---|---|
| VGA_R[9:0] | 10-bit Red level |
| VGA_G[9:0] | 10-bit Green level |
| VGA_B[9:0] | 10-bit Blue level |
| VGA_CLK | VGA Clock |
| VGA_BLANK | VGA BLANK |
| VGA_HS | VGA H_SYNC |
| VGA_VS | VGA V_SYNC |
| VGA_SYNC | VGA SYNC |
See DE2_pin_assignments.csv, a comma-delimited file
that matches "standard" descriptive names to actual FPGA pin locations. This file can be
directly opened in Microsoft Excel.
Maintained by John Loomis,
last updated 17 April 2007 References
Analog Devices ADV7123 video DAC
datasheet (pdf)
DE2 User Manual, version 1.4, 2006. (pdf)