The DE2 board includes two oscillators that produce 27 MHz and 50 MHz clock signals. The board also includes an SMA connector which can be used to connect an external clock source to the board. The schematic of the clock circuitry is shown in Figure 1, and the associated pin assignments appear in Table 1.
The 27-MHz clock is fed to the FPGA from the TV decoder chip. The
chip has an active-low reset signal that inhibits the clock when it is
asserted to a low logic level. To get the 27-MHz clock to appear on
the input pin, the TV decoder chip's reset signal (TD_RESET, PIN_C4 on
the FPGA) must be asserted to a high logic level. This means you need
TD_RESET as an output list and include the
assign TD_RESET = 1'b1;
Figure 1. Clock schematic
Table 1. Pin assignments for the clock inputs.
|CLOCK_27||27 MHz clock input|
|CLOCK_50||50 MHz clock input|
|EXT_CLOCK||External (SMA) clock input|
See DE2_pin_assignments.csv, a comma-delimited file that matches "standard" descriptive names to actual FPGA pin locations. This file can be directly opened in Microsoft Excel.
DE2 User Manual, version 1.4, 2006. (pdf)
Maintained by John Loomis, last updated 17 April 2007