Figure 1. USB (ISP1362) host and device schematic.
The DE2 board provides both USB host and device interfaces using the Philips ISP1362 single-chip USB controller. The host and device controllers are compliant with the Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). Figure 1 shows the schematic diagram of the USB circuitry; the pin assignments for the associated interface are listed in Table 1.
Detailed information for using the ISP1362 device is available in its datasheet and programming guide; both documents can be found in the ISP1362 references below. The most challenging part of a USB application is in the design of the software driver needed. Two complete examples of USB drivers, for both host and device applications, can be found in Sections 5.3 and 5.4. These demonstrations provide examples of software drivers for the Nios II processor.
Figure 1. USB (ISP1362) host and device schematic.
Table 1. USB (ISP1362) signal assignments
| Signal Name | Description |
|---|---|
| OTG_ADDR[1:0] | ISP1362 Address[1:0] |
| OTG_DATA[15:0] | ISP1362 Data[15:0] |
| OTG_CS_N | ISP1362 Chip Select |
| OTG_RD_N | ISP1362 Read |
| OTG_WR_N | ISP1362 Write |
| OTG_RST_N | ISP1362 Reset |
| OTG_INT0 | ISP1362 Interrupt 0 |
| OTG_INT1 | ISP1362 Interrupt 1 |
| OTG_DACK0_N | ISP1362 DMA Acknowledge 0 |
| OTG_DACK1_N | ISP1362 DMA Acknowledge 1 |
| OTG_DREQ0 | ISP1362 DMA Request 0 |
| OTG_DREQ1 | ISP1362 DMA Request 1 |
| OTG_FSPEED | USB Full Speed, 0 = Enable, Z = Disable |
| OTG_LSPEED | USB Low Speed, 0 = Enable, Z = Disable |
See DE2_pin_assignments.csv, a comma-delimited file
that matches "standard" descriptive names to actual FPGA pin locations. This file can be
directly opened in Microsoft Excel.
Maintained by John Loomis,
last updated 18 April 2007 References
ISP1362 Universal Serial Bus Controller, datasheet
ISP1362 Embedded Programming Guide,
(pdf)
DE2 User Manual, version 1.4, 2006. (pdf)