Download DE2 control panel files (zip file)
The DE2 board comes with a Control Panel facility that allows a user to access various components on the board through a USB connection from a host computer. This document shows how to setup the control panel, presents some of the basic functions of the Control Panel, and describes its structure in block diagram form.
To run the Control Panel application, you must configure the Cyclone II FPGA by downloading DE2_USB_API.sof into the FPGA and also execute DE2_control_panel.exe on the host computer.
Both of these files are available on the DE2 System CD-ROM that accompanies the DE2 board, in the directory DE2_control_panel. They are also available in the link at the top of the page. Of course, these files may already have been installed to some other location on your computer system.
To activate the Control Panel, perform the following steps:
Figure 1. Quartus II Programmer window.
Figure 2. The DE2 Control Panel.
The concept of the DE2 Control Panel is illustrated in Figure 3. The IP that performs the control functions is implemented in the FPGA device. It communicates with the Control Panel window, which is active on the host computer, via the USB Blaster link. The graphical interface is used to issue commands to the control circuitry. The provided IP handles all requests and performs data transfers between the computer and the DE2 board.
Figure 3. The DE2 Control Panel concept.
The DE2 Control Panel can be used to change the values displayed on 7-segment displays, light up LEDs, talk to the PS/2 keyboard, read/write the SRAM, Flash Memory and SDRAM, load an image pattern to display as VGA output, load music to the memory and play music via the audio DAC. The feature of reading/writing a byte or an entire file from/to the Flash Memory allows the user to develop multimedia applications (Flash Audio Player, Flash Picture Viewer) without worrying about how to build a Flash Memory Programmer.
A simple function of the Control Panel is to allow setting the values displayed on LEDs, 7-segment displays, and the LCD character display.
In the window shown in Figure 2, the values to be displayed by the 7-segment displays (which are named HEX7-0) can be entered into the corresponding boxes and displayed by pressing the Set button. A keyboard connected to the PS/2 port can be used to type text that will be displayed on the LCD display.
Choosing the LED & LCD tab leads to the window in Figure 4. Here, you can turn the individual LEDs on by selecting them and pressing the Set button. Text can be written to the LCD display by typing it in the LCD box and pressing the corresponding Set button.
The ability to set arbitrary values into simple display devices is not needed in typical design activities. However, it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected. Thus, it can be used for troubleshooting purposes.
Figure 4. Controlling LEDs and the LCD display.
The Control Panel can be used to write/read data to/from the SDRAM and SRAM chips on the DE2 board. We will describe how the SDRAM may be accessed; the same approach is used to access the SRAM. Click on the SDRAM tab to reach the window in Figure 5.
Figure 5. Accessing the SDRAM.
A 16-bit word can be written into the SDRAM by entering the address of the desired location, specifying the data to be written, and pressing the Write button. Contents of the location can be read by pressing the Read button. Figure 5 depicts the result of writing the hexadecimal value 6CA into location 200, followed by reading the same location.
The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows:
The Control Panel also supports loading files with a .hex extension. Files with a .hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values. For example, a file containing the line
0123456789ABCDEFdefines four 16-bit values: 0123, 4567, 89AB, CDEF. These values will be loaded consecutively into the memory.
The Sequential Read function is used to read the contents of the SDRAM and place them into a file as follows:
The Control Panel can be used to write/read data to/from the Flash memory chip on the DE2 board.
It can be used to:
Note the following characteristics of the Flash memory:
To open the Flash memory control window, shown in Figure 6, select the FLASH tab in the Control Panel.
Figure 6. Flash memory control window.
A byte of data can be written into a random location on the Flash chip as follows:
To read a byte of data from a random location, enter the address of the location and click on the Read button. The rDATA box will display the data read back from the address specified.
The Sequential Write function is used to load a file into the Flash chip as follows:
The Sequential Read function is used to read the data stored in the Flash memory and write this data into a file as follows:
The DE2 Control Panel facility communicates with a circuit that is instantiated in the Cyclone II FPGA. This circuit is specified in Verilog code, which makes it possible for a knowledgeable user to change the functionality of the Control Panel. The code is located inside the DE2_demonstrations directory on the DE2 System CD-ROM.
To run the Control Panel, the user must first set it up as explained earlier. Figure 7 depicts the structure of the Control Panel. Each input/output device is controlled by a controller instantiated in the FPGA chip. The communication with the PC is done via the USB Blaster link. A Command Controller circuit interprets the commands received from the PC and performs the appropriate actions. The SDRAM, SRAM, and Flash Memory controllers have three user-selectable asynchronous ports in addition to the Host port that provides a link with the Command Controller. The connection between the VGA DAC Controller and the FPGA memory allows displaying of the default image shown on the left side of the figure, which is stored in an M4K block in the Cyclone II chip. The connection between the Audio DAC Controller and a lookup table in the FPGA is used to produce a test audio signal of 1 kHz.
To let users implement and test their IP cores (written in Verilog) without requiring them to implement complex API/Host control software and memory (SRAM/SDRAM/Flash) controllers, we provide an integrated control environment consisting of a software controller in C++, a USB command controller, and a multi-port SRAM/SDRAM/Flash controller.
Figure 7. The DE2 Control Panel block diagram.
Users can connect circuits of their own design to one of the User Ports of the SRAM/SDRAM/Flash controller. Then, they can download binary data into the SRAM/SDRAM/Flash. Once the data is downloaded to the SDRAM/Flash, users can configure the memory controllers so that their circuits can read/write the SDRAM/Flash via the User Ports connected.
Maintained by John Loomis, last updated 8 November 2008