nios2lab1.v
module nios2lab1( // Clock Input (50 MHz) input CLOCK_50, // Push Buttons input [3:0] KEY, // DPDT Switches input [17:0] SW, // 7-SEG Displays output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, // LEDs output [8:0] LEDG, // LED Green[8:0] output [17:0] LEDR, // LED Red[17:0] // GPIO Connections inout [35:0] GPIO_0, GPIO_1 ); // set all inout ports to tri-state assign GPIO_0 = 36'hzzzzzzzzz; assign GPIO_1 = 36'hzzzzzzzzz; wire RST; assign RST = KEY[0]; // Connect dip switches to red LEDS assign LEDR[17:0] = SW[17:0]; wire [31:0] inport, outport; assign inport[20:18] = KEY[3:1]; assign inport[17:0] = SW; assign inport[31:21] = 0; //assign outport = inport; // map to 7-segment displays, blank leading zeros wire [7:0] bctl; hex_7seg_blanking dsp7(outport[31:28],HEX7,1'b1,bctl[0]); hex_7seg_blanking dsp6(outport[27:24],HEX6,bctl[0],bctl[1]); hex_7seg_blanking dsp5(outport[23:20],HEX5,bctl[1],bctl[2]); hex_7seg_blanking dsp4(outport[19:16],HEX4,bctl[2],bctl[3]); hex_7seg_blanking dsp3(outport[15:12],HEX3,bctl[3],bctl[4]); hex_7seg_blanking dsp2(outport[11:8] ,HEX2,bctl[4],bctl[5]); hex_7seg_blanking dsp1(outport[7:4] ,HEX1,bctl[5],bctl[6]); hex_7seg_blanking dsp0(outport[3:0] ,HEX0,bctl[6],bctl[7]); // instantiate our cpu cpu1 cpu1( // 1) global signals: .clk(CLOCK_50), .reset_n(RST), // the_pio_0 .in_port_to_the_pio(inport), .out_port_from_the_pio(outport) ); endmodule
cpu1.v
//megafunction wizard: %Altera SOPC Builder% //GENERATION: STANDARD //VERSION: WM1.0 //Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_jtag_debug_module_arbitrator ( // inputs: clk, cpu_data_master_address_to_slave, cpu_data_master_byteenable, cpu_data_master_debugaccess, cpu_data_master_latency_counter, cpu_data_master_read, cpu_data_master_write, cpu_data_master_writedata, cpu_instruction_master_address_to_slave, cpu_instruction_master_latency_counter, cpu_instruction_master_read, cpu_jtag_debug_module_readdata, cpu_jtag_debug_module_resetrequest, reset_n, // outputs: cpu_data_master_granted_cpu_jtag_debug_module, cpu_data_master_qualified_request_cpu_jtag_debug_module, cpu_data_master_read_data_valid_cpu_jtag_debug_module, cpu_data_master_requests_cpu_jtag_debug_module, cpu_instruction_master_granted_cpu_jtag_debug_module, cpu_instruction_master_qualified_request_cpu_jtag_debug_module, cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, cpu_instruction_master_requests_cpu_jtag_debug_module, cpu_jtag_debug_module_address, cpu_jtag_debug_module_begintransfer, cpu_jtag_debug_module_byteenable, cpu_jtag_debug_module_chipselect, cpu_jtag_debug_module_debugaccess, cpu_jtag_debug_module_readdata_from_sa, cpu_jtag_debug_module_reset, cpu_jtag_debug_module_reset_n, cpu_jtag_debug_module_resetrequest_from_sa, cpu_jtag_debug_module_write, cpu_jtag_debug_module_writedata, d1_cpu_jtag_debug_module_end_xfer ) /* synthesis auto_dissolve = "FALSE" */ ; output cpu_data_master_granted_cpu_jtag_debug_module; output cpu_data_master_qualified_request_cpu_jtag_debug_module; output cpu_data_master_read_data_valid_cpu_jtag_debug_module; output cpu_data_master_requests_cpu_jtag_debug_module; output cpu_instruction_master_granted_cpu_jtag_debug_module; output cpu_instruction_master_qualified_request_cpu_jtag_debug_module; output cpu_instruction_master_read_data_valid_cpu_jtag_debug_module; output cpu_instruction_master_requests_cpu_jtag_debug_module; output [ 8: 0] cpu_jtag_debug_module_address; output cpu_jtag_debug_module_begintransfer; output [ 3: 0] cpu_jtag_debug_module_byteenable; output cpu_jtag_debug_module_chipselect; output cpu_jtag_debug_module_debugaccess; output [ 31: 0] cpu_jtag_debug_module_readdata_from_sa; output cpu_jtag_debug_module_reset; output cpu_jtag_debug_module_reset_n; output cpu_jtag_debug_module_resetrequest_from_sa; output cpu_jtag_debug_module_write; output [ 31: 0] cpu_jtag_debug_module_writedata; output d1_cpu_jtag_debug_module_end_xfer; input clk; input [ 16: 0] cpu_data_master_address_to_slave; input [ 3: 0] cpu_data_master_byteenable; input cpu_data_master_debugaccess; input cpu_data_master_latency_counter; input cpu_data_master_read; input cpu_data_master_write; input [ 31: 0] cpu_data_master_writedata; input [ 16: 0] cpu_instruction_master_address_to_slave; input cpu_instruction_master_latency_counter; input cpu_instruction_master_read; input [ 31: 0] cpu_jtag_debug_module_readdata; input cpu_jtag_debug_module_resetrequest; input reset_n; wire cpu_data_master_arbiterlock; wire cpu_data_master_arbiterlock2; wire cpu_data_master_continuerequest; wire cpu_data_master_granted_cpu_jtag_debug_module; wire cpu_data_master_qualified_request_cpu_jtag_debug_module; wire cpu_data_master_read_data_valid_cpu_jtag_debug_module; wire cpu_data_master_requests_cpu_jtag_debug_module; wire cpu_data_master_saved_grant_cpu_jtag_debug_module; wire cpu_instruction_master_arbiterlock; wire cpu_instruction_master_arbiterlock2; wire cpu_instruction_master_continuerequest; wire cpu_instruction_master_granted_cpu_jtag_debug_module; wire cpu_instruction_master_qualified_request_cpu_jtag_debug_module; wire cpu_instruction_master_read_data_valid_cpu_jtag_debug_module; wire cpu_instruction_master_requests_cpu_jtag_debug_module; wire cpu_instruction_master_saved_grant_cpu_jtag_debug_module; wire [ 8: 0] cpu_jtag_debug_module_address; wire cpu_jtag_debug_module_allgrants; wire cpu_jtag_debug_module_allow_new_arb_cycle; wire cpu_jtag_debug_module_any_bursting_master_saved_grant; wire cpu_jtag_debug_module_any_continuerequest; reg [ 1: 0] cpu_jtag_debug_module_arb_addend; wire cpu_jtag_debug_module_arb_counter_enable; reg cpu_jtag_debug_module_arb_share_counter; wire cpu_jtag_debug_module_arb_share_counter_next_value; wire cpu_jtag_debug_module_arb_share_set_values; wire [ 1: 0] cpu_jtag_debug_module_arb_winner; wire cpu_jtag_debug_module_arbitration_holdoff_internal; wire cpu_jtag_debug_module_beginbursttransfer_internal; wire cpu_jtag_debug_module_begins_xfer; wire cpu_jtag_debug_module_begintransfer; wire [ 3: 0] cpu_jtag_debug_module_byteenable; wire cpu_jtag_debug_module_chipselect; wire [ 3: 0] cpu_jtag_debug_module_chosen_master_double_vector; wire [ 1: 0] cpu_jtag_debug_module_chosen_master_rot_left; wire cpu_jtag_debug_module_debugaccess; wire cpu_jtag_debug_module_end_xfer; wire cpu_jtag_debug_module_firsttransfer; wire [ 1: 0] cpu_jtag_debug_module_grant_vector; wire cpu_jtag_debug_module_in_a_read_cycle; wire cpu_jtag_debug_module_in_a_write_cycle; wire [ 1: 0] cpu_jtag_debug_module_master_qreq_vector; wire cpu_jtag_debug_module_non_bursting_master_requests; wire [ 31: 0] cpu_jtag_debug_module_readdata_from_sa; reg cpu_jtag_debug_module_reg_firsttransfer; wire cpu_jtag_debug_module_reset; wire cpu_jtag_debug_module_reset_n; wire cpu_jtag_debug_module_resetrequest_from_sa; reg [ 1: 0] cpu_jtag_debug_module_saved_chosen_master_vector; reg cpu_jtag_debug_module_slavearbiterlockenable; wire cpu_jtag_debug_module_slavearbiterlockenable2; wire cpu_jtag_debug_module_unreg_firsttransfer; wire cpu_jtag_debug_module_waits_for_read; wire cpu_jtag_debug_module_waits_for_write; wire cpu_jtag_debug_module_write; wire [ 31: 0] cpu_jtag_debug_module_writedata; reg d1_cpu_jtag_debug_module_end_xfer; reg d1_reasons_to_wait; reg enable_nonzero_assertions; wire end_xfer_arb_share_counter_term_cpu_jtag_debug_module; wire in_a_read_cycle; wire in_a_write_cycle; reg last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module; reg last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module; wire [ 16: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master; wire [ 16: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master; wire wait_for_cpu_jtag_debug_module_counter; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d1_reasons_to_wait <= 0; else if (1) d1_reasons_to_wait <= ~cpu_jtag_debug_module_end_xfer; end assign cpu_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cpu_jtag_debug_module | cpu_instruction_master_qualified_request_cpu_jtag_debug_module)); //assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata; assign cpu_data_master_requests_cpu_jtag_debug_module = ({cpu_data_master_address_to_slave[16 : 11] , 11'b0} == 17'h10800) & (cpu_data_master_read | cpu_data_master_write); //cpu_jtag_debug_module_arb_share_counter set values, which is an e_mux assign cpu_jtag_debug_module_arb_share_set_values = 1; //cpu_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux assign cpu_jtag_debug_module_non_bursting_master_requests = cpu_data_master_requests_cpu_jtag_debug_module | cpu_instruction_master_requests_cpu_jtag_debug_module | cpu_data_master_requests_cpu_jtag_debug_module | cpu_instruction_master_requests_cpu_jtag_debug_module; //cpu_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux assign cpu_jtag_debug_module_any_bursting_master_saved_grant = 0; //cpu_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign assign cpu_jtag_debug_module_arb_share_counter_next_value = cpu_jtag_debug_module_firsttransfer ? (cpu_jtag_debug_module_arb_share_set_values - 1) : |cpu_jtag_debug_module_arb_share_counter ? (cpu_jtag_debug_module_arb_share_counter - 1) : 0; //cpu_jtag_debug_module_allgrants all slave grants, which is an e_mux assign cpu_jtag_debug_module_allgrants = |cpu_jtag_debug_module_grant_vector | |cpu_jtag_debug_module_grant_vector | |cpu_jtag_debug_module_grant_vector | |cpu_jtag_debug_module_grant_vector; //cpu_jtag_debug_module_end_xfer assignment, which is an e_assign assign cpu_jtag_debug_module_end_xfer = ~(cpu_jtag_debug_module_waits_for_read | cpu_jtag_debug_module_waits_for_write); //end_xfer_arb_share_counter_term_cpu_jtag_debug_module arb share counter enable term, which is an e_assign assign end_xfer_arb_share_counter_term_cpu_jtag_debug_module = cpu_jtag_debug_module_end_xfer & (~cpu_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle); //cpu_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign assign cpu_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & cpu_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests); //cpu_jtag_debug_module_arb_share_counter counter, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_jtag_debug_module_arb_share_counter <= 0; else if (cpu_jtag_debug_module_arb_counter_enable) cpu_jtag_debug_module_arb_share_counter <= cpu_jtag_debug_module_arb_share_counter_next_value; end //cpu_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_jtag_debug_module_slavearbiterlockenable <= 0; else if ((|cpu_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests)) cpu_jtag_debug_module_slavearbiterlockenable <= |cpu_jtag_debug_module_arb_share_counter_next_value; end //cpu/data_master cpu/jtag_debug_module arbiterlock, which is an e_assign assign cpu_data_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_data_master_continuerequest; //cpu_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign assign cpu_jtag_debug_module_slavearbiterlockenable2 = |cpu_jtag_debug_module_arb_share_counter_next_value; //cpu/data_master cpu/jtag_debug_module arbiterlock2, which is an e_assign assign cpu_data_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_data_master_continuerequest; //cpu/instruction_master cpu/jtag_debug_module arbiterlock, which is an e_assign assign cpu_instruction_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_instruction_master_continuerequest; //cpu/instruction_master cpu/jtag_debug_module arbiterlock2, which is an e_assign assign cpu_instruction_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_instruction_master_continuerequest; //cpu/instruction_master granted cpu/jtag_debug_module last time, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= 0; else if (1) last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= cpu_instruction_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_instruction_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module; end //cpu_instruction_master_continuerequest continued request, which is an e_mux assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module & cpu_instruction_master_requests_cpu_jtag_debug_module; //cpu_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux assign cpu_jtag_debug_module_any_continuerequest = cpu_instruction_master_continuerequest | cpu_data_master_continuerequest; assign cpu_data_master_qualified_request_cpu_jtag_debug_module = cpu_data_master_requests_cpu_jtag_debug_module & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0))) | cpu_instruction_master_arbiterlock); //local readdatavalid cpu_data_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux assign cpu_data_master_read_data_valid_cpu_jtag_debug_module = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read & ~cpu_jtag_debug_module_waits_for_read; //cpu_jtag_debug_module_writedata mux, which is an e_mux assign cpu_jtag_debug_module_writedata = cpu_data_master_writedata; //mux cpu_jtag_debug_module_debugaccess, which is an e_mux assign cpu_jtag_debug_module_debugaccess = cpu_data_master_debugaccess; assign cpu_instruction_master_requests_cpu_jtag_debug_module = (({cpu_instruction_master_address_to_slave[16 : 11] , 11'b0} == 17'h10800) & (cpu_instruction_master_read)) & cpu_instruction_master_read; //cpu/data_master granted cpu/jtag_debug_module last time, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= 0; else if (1) last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= cpu_data_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_data_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module; end //cpu_data_master_continuerequest continued request, which is an e_mux assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module & cpu_data_master_requests_cpu_jtag_debug_module; assign cpu_instruction_master_qualified_request_cpu_jtag_debug_module = cpu_instruction_master_requests_cpu_jtag_debug_module & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0))) | cpu_data_master_arbiterlock); //local readdatavalid cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux assign cpu_instruction_master_read_data_valid_cpu_jtag_debug_module = cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read & ~cpu_jtag_debug_module_waits_for_read; //allow new arb cycle for cpu/jtag_debug_module, which is an e_assign assign cpu_jtag_debug_module_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock; //cpu/instruction_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign assign cpu_jtag_debug_module_master_qreq_vector[0] = cpu_instruction_master_qualified_request_cpu_jtag_debug_module; //cpu/instruction_master grant cpu/jtag_debug_module, which is an e_assign assign cpu_instruction_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[0]; //cpu/instruction_master saved-grant cpu/jtag_debug_module, which is an e_assign assign cpu_instruction_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[0] && cpu_instruction_master_requests_cpu_jtag_debug_module; //cpu/data_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign assign cpu_jtag_debug_module_master_qreq_vector[1] = cpu_data_master_qualified_request_cpu_jtag_debug_module; //cpu/data_master grant cpu/jtag_debug_module, which is an e_assign assign cpu_data_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[1]; //cpu/data_master saved-grant cpu/jtag_debug_module, which is an e_assign assign cpu_data_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[1] && cpu_data_master_requests_cpu_jtag_debug_module; //cpu/jtag_debug_module chosen-master double-vector, which is an e_assign assign cpu_jtag_debug_module_chosen_master_double_vector = {cpu_jtag_debug_module_master_qreq_vector, cpu_jtag_debug_module_master_qreq_vector} & ({~cpu_jtag_debug_module_master_qreq_vector, ~cpu_jtag_debug_module_master_qreq_vector} + cpu_jtag_debug_module_arb_addend); //stable onehot encoding of arb winner assign cpu_jtag_debug_module_arb_winner = (cpu_jtag_debug_module_allow_new_arb_cycle & | cpu_jtag_debug_module_grant_vector) ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector; //saved cpu_jtag_debug_module_grant_vector, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_jtag_debug_module_saved_chosen_master_vector <= 0; else if (cpu_jtag_debug_module_allow_new_arb_cycle) cpu_jtag_debug_module_saved_chosen_master_vector <= |cpu_jtag_debug_module_grant_vector ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector; end //onehot encoding of chosen master assign cpu_jtag_debug_module_grant_vector = {(cpu_jtag_debug_module_chosen_master_double_vector[1] | cpu_jtag_debug_module_chosen_master_double_vector[3]), (cpu_jtag_debug_module_chosen_master_double_vector[0] | cpu_jtag_debug_module_chosen_master_double_vector[2])}; //cpu/jtag_debug_module chosen master rotated left, which is an e_assign assign cpu_jtag_debug_module_chosen_master_rot_left = (cpu_jtag_debug_module_arb_winner << 1) ? (cpu_jtag_debug_module_arb_winner << 1) : 1; //cpu/jtag_debug_module's addend for next-master-grant always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_jtag_debug_module_arb_addend <= 1; else if (|cpu_jtag_debug_module_grant_vector) cpu_jtag_debug_module_arb_addend <= cpu_jtag_debug_module_end_xfer? cpu_jtag_debug_module_chosen_master_rot_left : cpu_jtag_debug_module_grant_vector; end assign cpu_jtag_debug_module_begintransfer = cpu_jtag_debug_module_begins_xfer; //assign lhs ~cpu_jtag_debug_module_reset of type reset_n to cpu_jtag_debug_module_reset_n, which is an e_assign assign cpu_jtag_debug_module_reset = ~cpu_jtag_debug_module_reset_n; //cpu_jtag_debug_module_reset_n assignment, which is an e_assign assign cpu_jtag_debug_module_reset_n = reset_n; //assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest; assign cpu_jtag_debug_module_chipselect = cpu_data_master_granted_cpu_jtag_debug_module | cpu_instruction_master_granted_cpu_jtag_debug_module; //cpu_jtag_debug_module_firsttransfer first transaction, which is an e_assign assign cpu_jtag_debug_module_firsttransfer = cpu_jtag_debug_module_begins_xfer ? cpu_jtag_debug_module_unreg_firsttransfer : cpu_jtag_debug_module_reg_firsttransfer; //cpu_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign assign cpu_jtag_debug_module_unreg_firsttransfer = ~(cpu_jtag_debug_module_slavearbiterlockenable & cpu_jtag_debug_module_any_continuerequest); //cpu_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_jtag_debug_module_reg_firsttransfer <= 1'b1; else if (cpu_jtag_debug_module_begins_xfer) cpu_jtag_debug_module_reg_firsttransfer <= cpu_jtag_debug_module_unreg_firsttransfer; end //cpu_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign assign cpu_jtag_debug_module_beginbursttransfer_internal = cpu_jtag_debug_module_begins_xfer; //cpu_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign assign cpu_jtag_debug_module_arbitration_holdoff_internal = cpu_jtag_debug_module_begins_xfer & cpu_jtag_debug_module_firsttransfer; //cpu_jtag_debug_module_write assignment, which is an e_mux assign cpu_jtag_debug_module_write = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write; assign shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master = cpu_data_master_address_to_slave; //cpu_jtag_debug_module_address mux, which is an e_mux assign cpu_jtag_debug_module_address = (cpu_data_master_granted_cpu_jtag_debug_module)? (shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master >> 2) : (shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master >> 2); assign shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master = cpu_instruction_master_address_to_slave; //d1_cpu_jtag_debug_module_end_xfer register, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d1_cpu_jtag_debug_module_end_xfer <= 1; else if (1) d1_cpu_jtag_debug_module_end_xfer <= cpu_jtag_debug_module_end_xfer; end //cpu_jtag_debug_module_waits_for_read in a cycle, which is an e_mux assign cpu_jtag_debug_module_waits_for_read = cpu_jtag_debug_module_in_a_read_cycle & cpu_jtag_debug_module_begins_xfer; //cpu_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign assign cpu_jtag_debug_module_in_a_read_cycle = (cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read) | (cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read); //in_a_read_cycle assignment, which is an e_mux assign in_a_read_cycle = cpu_jtag_debug_module_in_a_read_cycle; //cpu_jtag_debug_module_waits_for_write in a cycle, which is an e_mux assign cpu_jtag_debug_module_waits_for_write = cpu_jtag_debug_module_in_a_write_cycle & 0; //cpu_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign assign cpu_jtag_debug_module_in_a_write_cycle = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write; //in_a_write_cycle assignment, which is an e_mux assign in_a_write_cycle = cpu_jtag_debug_module_in_a_write_cycle; assign wait_for_cpu_jtag_debug_module_counter = 0; //cpu_jtag_debug_module_byteenable byte enable port mux, which is an e_mux assign cpu_jtag_debug_module_byteenable = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_byteenable : -1; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //cpu/jtag_debug_module enable non-zero assertions, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) enable_nonzero_assertions <= 0; else if (1) enable_nonzero_assertions <= 1'b1; end //grant signals are active simultaneously, which is an e_process always @(posedge clk) begin if (cpu_data_master_granted_cpu_jtag_debug_module + cpu_instruction_master_granted_cpu_jtag_debug_module > 1) begin $write("%0d ns: > 1 of grant signals are active simultaneously", $time); $stop; end end //saved_grant signals are active simultaneously, which is an e_process always @(posedge clk) begin if (cpu_data_master_saved_grant_cpu_jtag_debug_module + cpu_instruction_master_saved_grant_cpu_jtag_debug_module > 1) begin $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time); $stop; end end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_data_master_arbitrator ( // inputs: clk, cpu_data_master_address, cpu_data_master_debugaccess, cpu_data_master_granted_cpu_jtag_debug_module, cpu_data_master_granted_jtag_uart_avalon_jtag_slave, cpu_data_master_granted_onchip_mem_s1, cpu_data_master_granted_pio_s1, cpu_data_master_qualified_request_cpu_jtag_debug_module, cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave, cpu_data_master_qualified_request_onchip_mem_s1, cpu_data_master_qualified_request_pio_s1, cpu_data_master_read, cpu_data_master_read_data_valid_cpu_jtag_debug_module, cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave, cpu_data_master_read_data_valid_onchip_mem_s1, cpu_data_master_read_data_valid_pio_s1, cpu_data_master_requests_cpu_jtag_debug_module, cpu_data_master_requests_jtag_uart_avalon_jtag_slave, cpu_data_master_requests_onchip_mem_s1, cpu_data_master_requests_pio_s1, cpu_data_master_write, cpu_data_master_writedata, cpu_jtag_debug_module_readdata_from_sa, d1_cpu_jtag_debug_module_end_xfer, d1_jtag_uart_avalon_jtag_slave_end_xfer, d1_onchip_mem_s1_end_xfer, d1_pio_s1_end_xfer, jtag_uart_avalon_jtag_slave_irq_from_sa, jtag_uart_avalon_jtag_slave_readdata_from_sa, jtag_uart_avalon_jtag_slave_waitrequest_from_sa, onchip_mem_s1_readdata_from_sa, pio_s1_readdata_from_sa, reset_n, // outputs: cpu_data_master_address_to_slave, cpu_data_master_irq, cpu_data_master_latency_counter, cpu_data_master_readdata, cpu_data_master_readdatavalid, cpu_data_master_waitrequest ) /* synthesis auto_dissolve = "FALSE" */ ; output [ 16: 0] cpu_data_master_address_to_slave; output [ 31: 0] cpu_data_master_irq; output cpu_data_master_latency_counter; output [ 31: 0] cpu_data_master_readdata; output cpu_data_master_readdatavalid; output cpu_data_master_waitrequest; input clk; input [ 16: 0] cpu_data_master_address; input cpu_data_master_debugaccess; input cpu_data_master_granted_cpu_jtag_debug_module; input cpu_data_master_granted_jtag_uart_avalon_jtag_slave; input cpu_data_master_granted_onchip_mem_s1; input cpu_data_master_granted_pio_s1; input cpu_data_master_qualified_request_cpu_jtag_debug_module; input cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave; input cpu_data_master_qualified_request_onchip_mem_s1; input cpu_data_master_qualified_request_pio_s1; input cpu_data_master_read; input cpu_data_master_read_data_valid_cpu_jtag_debug_module; input cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave; input cpu_data_master_read_data_valid_onchip_mem_s1; input cpu_data_master_read_data_valid_pio_s1; input cpu_data_master_requests_cpu_jtag_debug_module; input cpu_data_master_requests_jtag_uart_avalon_jtag_slave; input cpu_data_master_requests_onchip_mem_s1; input cpu_data_master_requests_pio_s1; input cpu_data_master_write; input [ 31: 0] cpu_data_master_writedata; input [ 31: 0] cpu_jtag_debug_module_readdata_from_sa; input d1_cpu_jtag_debug_module_end_xfer; input d1_jtag_uart_avalon_jtag_slave_end_xfer; input d1_onchip_mem_s1_end_xfer; input d1_pio_s1_end_xfer; input jtag_uart_avalon_jtag_slave_irq_from_sa; input [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa; input jtag_uart_avalon_jtag_slave_waitrequest_from_sa; input [ 31: 0] onchip_mem_s1_readdata_from_sa; input [ 31: 0] pio_s1_readdata_from_sa; input reset_n; reg active_and_waiting_last_time; reg [ 16: 0] cpu_data_master_address_last_time; wire [ 16: 0] cpu_data_master_address_to_slave; wire [ 31: 0] cpu_data_master_irq; wire cpu_data_master_is_granted_some_slave; reg cpu_data_master_latency_counter; reg cpu_data_master_read_but_no_slave_selected; reg cpu_data_master_read_last_time; wire [ 31: 0] cpu_data_master_readdata; wire cpu_data_master_readdatavalid; wire cpu_data_master_run; wire cpu_data_master_waitrequest; reg cpu_data_master_write_last_time; reg [ 31: 0] cpu_data_master_writedata_last_time; wire latency_load_value; wire p1_cpu_data_master_latency_counter; wire pre_flush_cpu_data_master_readdatavalid; wire r_0; //r_0 master_run cascaded wait assignment, which is an e_assign assign r_0 = 1 & (cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_requests_cpu_jtag_debug_module) & (cpu_data_master_granted_cpu_jtag_debug_module | ~cpu_data_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_read | (1 & ~d1_cpu_jtag_debug_module_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_onchip_mem_s1 | ~cpu_data_master_requests_onchip_mem_s1) & (cpu_data_master_granted_onchip_mem_s1 | ~cpu_data_master_qualified_request_onchip_mem_s1) & ((~cpu_data_master_qualified_request_onchip_mem_s1 | ~(cpu_data_master_read | cpu_data_master_write) | (1 & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_onchip_mem_s1 | ~(cpu_data_master_read | cpu_data_master_write) | (1 & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_pio_s1 | ~cpu_data_master_requests_pio_s1) & ((~cpu_data_master_qualified_request_pio_s1 | ~cpu_data_master_read | (1 & ~d1_pio_s1_end_xfer & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_pio_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))); //cascaded wait assignment, which is an e_assign assign cpu_data_master_run = r_0; //optimize select-logic by passing only those address bits which matter. assign cpu_data_master_address_to_slave = cpu_data_master_address[16 : 0]; //cpu_data_master_read_but_no_slave_selected assignment, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_data_master_read_but_no_slave_selected <= 0; else if (1) cpu_data_master_read_but_no_slave_selected <= cpu_data_master_read & cpu_data_master_run & ~cpu_data_master_is_granted_some_slave; end //some slave is getting selected, which is an e_mux assign cpu_data_master_is_granted_some_slave = cpu_data_master_granted_cpu_jtag_debug_module | cpu_data_master_granted_jtag_uart_avalon_jtag_slave | cpu_data_master_granted_onchip_mem_s1 | cpu_data_master_granted_pio_s1; //latent slave read data valids which may be flushed, which is an e_mux assign pre_flush_cpu_data_master_readdatavalid = cpu_data_master_read_data_valid_onchip_mem_s1; //latent slave read data valid which is not flushed, which is an e_mux assign cpu_data_master_readdatavalid = cpu_data_master_read_but_no_slave_selected | pre_flush_cpu_data_master_readdatavalid | cpu_data_master_read_data_valid_cpu_jtag_debug_module | cpu_data_master_read_but_no_slave_selected | pre_flush_cpu_data_master_readdatavalid | cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave | cpu_data_master_read_but_no_slave_selected | pre_flush_cpu_data_master_readdatavalid | cpu_data_master_read_but_no_slave_selected | pre_flush_cpu_data_master_readdatavalid | cpu_data_master_read_data_valid_pio_s1; //cpu/data_master readdata mux, which is an e_mux assign cpu_data_master_readdata = ({32 {~(cpu_data_master_qualified_request_cpu_jtag_debug_module & cpu_data_master_read)}} | cpu_jtag_debug_module_readdata_from_sa) & ({32 {~(cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave & cpu_data_master_read)}} | jtag_uart_avalon_jtag_slave_readdata_from_sa) & ({32 {~cpu_data_master_read_data_valid_onchip_mem_s1}} | onchip_mem_s1_readdata_from_sa) & ({32 {~(cpu_data_master_qualified_request_pio_s1 & cpu_data_master_read)}} | pio_s1_readdata_from_sa); //actual waitrequest port, which is an e_assign assign cpu_data_master_waitrequest = ~cpu_data_master_run; //latent max counter, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_data_master_latency_counter <= 0; else if (1) cpu_data_master_latency_counter <= p1_cpu_data_master_latency_counter; end //latency counter load mux, which is an e_mux assign p1_cpu_data_master_latency_counter = ((cpu_data_master_run & cpu_data_master_read))? latency_load_value : (cpu_data_master_latency_counter)? cpu_data_master_latency_counter - 1 : 0; //read latency load values, which is an e_mux assign latency_load_value = {1 {cpu_data_master_requests_onchip_mem_s1}} & 1; //irq assign, which is an e_assign assign cpu_data_master_irq = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, jtag_uart_avalon_jtag_slave_irq_from_sa}; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //cpu_data_master_address check against wait, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_data_master_address_last_time <= 0; else if (1) cpu_data_master_address_last_time <= cpu_data_master_address; end //cpu/data_master waited last time, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) active_and_waiting_last_time <= 0; else if (1) active_and_waiting_last_time <= cpu_data_master_waitrequest & (cpu_data_master_read | cpu_data_master_write); end //cpu_data_master_address matches last port_name, which is an e_process always @(active_and_waiting_last_time or cpu_data_master_address or cpu_data_master_address_last_time) begin if (active_and_waiting_last_time & (cpu_data_master_address != cpu_data_master_address_last_time)) begin $write("%0d ns: cpu_data_master_address did not heed wait!!!", $time); $stop; end end //cpu_data_master_read check against wait, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_data_master_read_last_time <= 0; else if (1) cpu_data_master_read_last_time <= cpu_data_master_read; end //cpu_data_master_read matches last port_name, which is an e_process always @(active_and_waiting_last_time or cpu_data_master_read or cpu_data_master_read_last_time) begin if (active_and_waiting_last_time & (cpu_data_master_read != cpu_data_master_read_last_time)) begin $write("%0d ns: cpu_data_master_read did not heed wait!!!", $time); $stop; end end //cpu_data_master_write check against wait, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_data_master_write_last_time <= 0; else if (1) cpu_data_master_write_last_time <= cpu_data_master_write; end //cpu_data_master_write matches last port_name, which is an e_process always @(active_and_waiting_last_time or cpu_data_master_write or cpu_data_master_write_last_time) begin if (active_and_waiting_last_time & (cpu_data_master_write != cpu_data_master_write_last_time)) begin $write("%0d ns: cpu_data_master_write did not heed wait!!!", $time); $stop; end end //cpu_data_master_writedata check against wait, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_data_master_writedata_last_time <= 0; else if (1) cpu_data_master_writedata_last_time <= cpu_data_master_writedata; end //cpu_data_master_writedata matches last port_name, which is an e_process always @(active_and_waiting_last_time or cpu_data_master_write or cpu_data_master_writedata or cpu_data_master_writedata_last_time) begin if (active_and_waiting_last_time & (cpu_data_master_writedata != cpu_data_master_writedata_last_time) & cpu_data_master_write) begin $write("%0d ns: cpu_data_master_writedata did not heed wait!!!", $time); $stop; end end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_instruction_master_arbitrator ( // inputs: clk, cpu_instruction_master_address, cpu_instruction_master_granted_cpu_jtag_debug_module, cpu_instruction_master_granted_onchip_mem_s1, cpu_instruction_master_qualified_request_cpu_jtag_debug_module, cpu_instruction_master_qualified_request_onchip_mem_s1, cpu_instruction_master_read, cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, cpu_instruction_master_read_data_valid_onchip_mem_s1, cpu_instruction_master_requests_cpu_jtag_debug_module, cpu_instruction_master_requests_onchip_mem_s1, cpu_jtag_debug_module_readdata_from_sa, d1_cpu_jtag_debug_module_end_xfer, d1_onchip_mem_s1_end_xfer, onchip_mem_s1_readdata_from_sa, reset_n, // outputs: cpu_instruction_master_address_to_slave, cpu_instruction_master_latency_counter, cpu_instruction_master_readdata, cpu_instruction_master_readdatavalid, cpu_instruction_master_waitrequest ) /* synthesis auto_dissolve = "FALSE" */ ; output [ 16: 0] cpu_instruction_master_address_to_slave; output cpu_instruction_master_latency_counter; output [ 31: 0] cpu_instruction_master_readdata; output cpu_instruction_master_readdatavalid; output cpu_instruction_master_waitrequest; input clk; input [ 16: 0] cpu_instruction_master_address; input cpu_instruction_master_granted_cpu_jtag_debug_module; input cpu_instruction_master_granted_onchip_mem_s1; input cpu_instruction_master_qualified_request_cpu_jtag_debug_module; input cpu_instruction_master_qualified_request_onchip_mem_s1; input cpu_instruction_master_read; input cpu_instruction_master_read_data_valid_cpu_jtag_debug_module; input cpu_instruction_master_read_data_valid_onchip_mem_s1; input cpu_instruction_master_requests_cpu_jtag_debug_module; input cpu_instruction_master_requests_onchip_mem_s1; input [ 31: 0] cpu_jtag_debug_module_readdata_from_sa; input d1_cpu_jtag_debug_module_end_xfer; input d1_onchip_mem_s1_end_xfer; input [ 31: 0] onchip_mem_s1_readdata_from_sa; input reset_n; reg active_and_waiting_last_time; reg [ 16: 0] cpu_instruction_master_address_last_time; wire [ 16: 0] cpu_instruction_master_address_to_slave; wire cpu_instruction_master_is_granted_some_slave; reg cpu_instruction_master_latency_counter; reg cpu_instruction_master_read_but_no_slave_selected; reg cpu_instruction_master_read_last_time; wire [ 31: 0] cpu_instruction_master_readdata; wire cpu_instruction_master_readdatavalid; wire cpu_instruction_master_run; wire cpu_instruction_master_waitrequest; wire latency_load_value; wire p1_cpu_instruction_master_latency_counter; wire pre_flush_cpu_instruction_master_readdatavalid; wire r_0; //r_0 master_run cascaded wait assignment, which is an e_assign assign r_0 = 1 & (cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_requests_cpu_jtag_debug_module) & (cpu_instruction_master_granted_cpu_jtag_debug_module | ~cpu_instruction_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_read | (1 & ~d1_cpu_jtag_debug_module_end_xfer & cpu_instruction_master_read))) & 1 & (cpu_instruction_master_qualified_request_onchip_mem_s1 | ~cpu_instruction_master_requests_onchip_mem_s1) & (cpu_instruction_master_granted_onchip_mem_s1 | ~cpu_instruction_master_qualified_request_onchip_mem_s1) & ((~cpu_instruction_master_qualified_request_onchip_mem_s1 | ~(cpu_instruction_master_read) | (1 & (cpu_instruction_master_read)))); //cascaded wait assignment, which is an e_assign assign cpu_instruction_master_run = r_0; //optimize select-logic by passing only those address bits which matter. assign cpu_instruction_master_address_to_slave = cpu_instruction_master_address[16 : 0]; //cpu_instruction_master_read_but_no_slave_selected assignment, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_instruction_master_read_but_no_slave_selected <= 0; else if (1) cpu_instruction_master_read_but_no_slave_selected <= cpu_instruction_master_read & cpu_instruction_master_run & ~cpu_instruction_master_is_granted_some_slave; end //some slave is getting selected, which is an e_mux assign cpu_instruction_master_is_granted_some_slave = cpu_instruction_master_granted_cpu_jtag_debug_module | cpu_instruction_master_granted_onchip_mem_s1; //latent slave read data valids which may be flushed, which is an e_mux assign pre_flush_cpu_instruction_master_readdatavalid = cpu_instruction_master_read_data_valid_onchip_mem_s1; //latent slave read data valid which is not flushed, which is an e_mux assign cpu_instruction_master_readdatavalid = cpu_instruction_master_read_but_no_slave_selected | pre_flush_cpu_instruction_master_readdatavalid | cpu_instruction_master_read_data_valid_cpu_jtag_debug_module | cpu_instruction_master_read_but_no_slave_selected | pre_flush_cpu_instruction_master_readdatavalid; //cpu/instruction_master readdata mux, which is an e_mux assign cpu_instruction_master_readdata = ({32 {~(cpu_instruction_master_qualified_request_cpu_jtag_debug_module & cpu_instruction_master_read)}} | cpu_jtag_debug_module_readdata_from_sa) & ({32 {~cpu_instruction_master_read_data_valid_onchip_mem_s1}} | onchip_mem_s1_readdata_from_sa); //actual waitrequest port, which is an e_assign assign cpu_instruction_master_waitrequest = ~cpu_instruction_master_run; //latent max counter, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_instruction_master_latency_counter <= 0; else if (1) cpu_instruction_master_latency_counter <= p1_cpu_instruction_master_latency_counter; end //latency counter load mux, which is an e_mux assign p1_cpu_instruction_master_latency_counter = ((cpu_instruction_master_run & cpu_instruction_master_read))? latency_load_value : (cpu_instruction_master_latency_counter)? cpu_instruction_master_latency_counter - 1 : 0; //read latency load values, which is an e_mux assign latency_load_value = {1 {cpu_instruction_master_requests_onchip_mem_s1}} & 1; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //cpu_instruction_master_address check against wait, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_instruction_master_address_last_time <= 0; else if (1) cpu_instruction_master_address_last_time <= cpu_instruction_master_address; end //cpu/instruction_master waited last time, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) active_and_waiting_last_time <= 0; else if (1) active_and_waiting_last_time <= cpu_instruction_master_waitrequest & (cpu_instruction_master_read); end //cpu_instruction_master_address matches last port_name, which is an e_process always @(active_and_waiting_last_time or cpu_instruction_master_address or cpu_instruction_master_address_last_time) begin if (active_and_waiting_last_time & (cpu_instruction_master_address != cpu_instruction_master_address_last_time)) begin $write("%0d ns: cpu_instruction_master_address did not heed wait!!!", $time); $stop; end end //cpu_instruction_master_read check against wait, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_instruction_master_read_last_time <= 0; else if (1) cpu_instruction_master_read_last_time <= cpu_instruction_master_read; end //cpu_instruction_master_read matches last port_name, which is an e_process always @(active_and_waiting_last_time or cpu_instruction_master_read or cpu_instruction_master_read_last_time) begin if (active_and_waiting_last_time & (cpu_instruction_master_read != cpu_instruction_master_read_last_time)) begin $write("%0d ns: cpu_instruction_master_read did not heed wait!!!", $time); $stop; end end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module jtag_uart_avalon_jtag_slave_arbitrator ( // inputs: clk, cpu_data_master_address_to_slave, cpu_data_master_latency_counter, cpu_data_master_read, cpu_data_master_write, cpu_data_master_writedata, jtag_uart_avalon_jtag_slave_dataavailable, jtag_uart_avalon_jtag_slave_irq, jtag_uart_avalon_jtag_slave_readdata, jtag_uart_avalon_jtag_slave_readyfordata, jtag_uart_avalon_jtag_slave_waitrequest, reset_n, // outputs: cpu_data_master_granted_jtag_uart_avalon_jtag_slave, cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave, cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave, cpu_data_master_requests_jtag_uart_avalon_jtag_slave, d1_jtag_uart_avalon_jtag_slave_end_xfer, jtag_uart_avalon_jtag_slave_address, jtag_uart_avalon_jtag_slave_chipselect, jtag_uart_avalon_jtag_slave_dataavailable_from_sa, jtag_uart_avalon_jtag_slave_irq_from_sa, jtag_uart_avalon_jtag_slave_read_n, jtag_uart_avalon_jtag_slave_readdata_from_sa, jtag_uart_avalon_jtag_slave_readyfordata_from_sa, jtag_uart_avalon_jtag_slave_reset_n, jtag_uart_avalon_jtag_slave_waitrequest_from_sa, jtag_uart_avalon_jtag_slave_write_n, jtag_uart_avalon_jtag_slave_writedata ) /* synthesis auto_dissolve = "FALSE" */ ; output cpu_data_master_granted_jtag_uart_avalon_jtag_slave; output cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave; output cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave; output cpu_data_master_requests_jtag_uart_avalon_jtag_slave; output d1_jtag_uart_avalon_jtag_slave_end_xfer; output jtag_uart_avalon_jtag_slave_address; output jtag_uart_avalon_jtag_slave_chipselect; output jtag_uart_avalon_jtag_slave_dataavailable_from_sa; output jtag_uart_avalon_jtag_slave_irq_from_sa; output jtag_uart_avalon_jtag_slave_read_n; output [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa; output jtag_uart_avalon_jtag_slave_readyfordata_from_sa; output jtag_uart_avalon_jtag_slave_reset_n; output jtag_uart_avalon_jtag_slave_waitrequest_from_sa; output jtag_uart_avalon_jtag_slave_write_n; output [ 31: 0] jtag_uart_avalon_jtag_slave_writedata; input clk; input [ 16: 0] cpu_data_master_address_to_slave; input cpu_data_master_latency_counter; input cpu_data_master_read; input cpu_data_master_write; input [ 31: 0] cpu_data_master_writedata; input jtag_uart_avalon_jtag_slave_dataavailable; input jtag_uart_avalon_jtag_slave_irq; input [ 31: 0] jtag_uart_avalon_jtag_slave_readdata; input jtag_uart_avalon_jtag_slave_readyfordata; input jtag_uart_avalon_jtag_slave_waitrequest; input reset_n; wire cpu_data_master_arbiterlock; wire cpu_data_master_arbiterlock2; wire cpu_data_master_continuerequest; wire cpu_data_master_granted_jtag_uart_avalon_jtag_slave; wire cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave; wire cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave; wire cpu_data_master_requests_jtag_uart_avalon_jtag_slave; wire cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave; reg d1_jtag_uart_avalon_jtag_slave_end_xfer; reg d1_reasons_to_wait; reg enable_nonzero_assertions; wire end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave; wire in_a_read_cycle; wire in_a_write_cycle; wire jtag_uart_avalon_jtag_slave_address; wire jtag_uart_avalon_jtag_slave_allgrants; wire jtag_uart_avalon_jtag_slave_allow_new_arb_cycle; wire jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant; wire jtag_uart_avalon_jtag_slave_any_continuerequest; wire jtag_uart_avalon_jtag_slave_arb_counter_enable; reg jtag_uart_avalon_jtag_slave_arb_share_counter; wire jtag_uart_avalon_jtag_slave_arb_share_counter_next_value; wire jtag_uart_avalon_jtag_slave_arb_share_set_values; wire jtag_uart_avalon_jtag_slave_beginbursttransfer_internal; wire jtag_uart_avalon_jtag_slave_begins_xfer; wire jtag_uart_avalon_jtag_slave_chipselect; wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa; wire jtag_uart_avalon_jtag_slave_end_xfer; wire jtag_uart_avalon_jtag_slave_firsttransfer; wire jtag_uart_avalon_jtag_slave_grant_vector; wire jtag_uart_avalon_jtag_slave_in_a_read_cycle; wire jtag_uart_avalon_jtag_slave_in_a_write_cycle; wire jtag_uart_avalon_jtag_slave_irq_from_sa; wire jtag_uart_avalon_jtag_slave_master_qreq_vector; wire jtag_uart_avalon_jtag_slave_non_bursting_master_requests; wire jtag_uart_avalon_jtag_slave_read_n; wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa; wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa; reg jtag_uart_avalon_jtag_slave_reg_firsttransfer; wire jtag_uart_avalon_jtag_slave_reset_n; reg jtag_uart_avalon_jtag_slave_slavearbiterlockenable; wire jtag_uart_avalon_jtag_slave_slavearbiterlockenable2; wire jtag_uart_avalon_jtag_slave_unreg_firsttransfer; wire jtag_uart_avalon_jtag_slave_waitrequest_from_sa; wire jtag_uart_avalon_jtag_slave_waits_for_read; wire jtag_uart_avalon_jtag_slave_waits_for_write; wire jtag_uart_avalon_jtag_slave_write_n; wire [ 31: 0] jtag_uart_avalon_jtag_slave_writedata; wire [ 16: 0] shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master; wire wait_for_jtag_uart_avalon_jtag_slave_counter; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d1_reasons_to_wait <= 0; else if (1) d1_reasons_to_wait <= ~jtag_uart_avalon_jtag_slave_end_xfer; end assign jtag_uart_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave)); //assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata; assign cpu_data_master_requests_jtag_uart_avalon_jtag_slave = ({cpu_data_master_address_to_slave[16 : 3] , 3'b0} == 17'h11010) & (cpu_data_master_read | cpu_data_master_write); //assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable; //assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata; //assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest; //jtag_uart_avalon_jtag_slave_arb_share_counter set values, which is an e_mux assign jtag_uart_avalon_jtag_slave_arb_share_set_values = 1; //jtag_uart_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux assign jtag_uart_avalon_jtag_slave_non_bursting_master_requests = cpu_data_master_requests_jtag_uart_avalon_jtag_slave; //jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux assign jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant = 0; //jtag_uart_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign assign jtag_uart_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_avalon_jtag_slave_firsttransfer ? (jtag_uart_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_avalon_jtag_slave_arb_share_counter ? (jtag_uart_avalon_jtag_slave_arb_share_counter - 1) : 0; //jtag_uart_avalon_jtag_slave_allgrants all slave grants, which is an e_mux assign jtag_uart_avalon_jtag_slave_allgrants = |jtag_uart_avalon_jtag_slave_grant_vector; //jtag_uart_avalon_jtag_slave_end_xfer assignment, which is an e_assign assign jtag_uart_avalon_jtag_slave_end_xfer = ~(jtag_uart_avalon_jtag_slave_waits_for_read | jtag_uart_avalon_jtag_slave_waits_for_write); //end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave arb share counter enable term, which is an e_assign assign end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave = jtag_uart_avalon_jtag_slave_end_xfer & (~jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle); //jtag_uart_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign assign jtag_uart_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & jtag_uart_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests); //jtag_uart_avalon_jtag_slave_arb_share_counter counter, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) jtag_uart_avalon_jtag_slave_arb_share_counter <= 0; else if (jtag_uart_avalon_jtag_slave_arb_counter_enable) jtag_uart_avalon_jtag_slave_arb_share_counter <= jtag_uart_avalon_jtag_slave_arb_share_counter_next_value; end //jtag_uart_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= 0; else if ((|jtag_uart_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests)) jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value; end //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock, which is an e_assign assign cpu_data_master_arbiterlock = jtag_uart_avalon_jtag_slave_slavearbiterlockenable & cpu_data_master_continuerequest; //jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign assign jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value; //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock2, which is an e_assign assign cpu_data_master_arbiterlock2 = jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest; //jtag_uart_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign assign jtag_uart_avalon_jtag_slave_any_continuerequest = 1; //cpu_data_master_continuerequest continued request, which is an e_assign assign cpu_data_master_continuerequest = 1; assign cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0)))); //local readdatavalid cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave, which is an e_mux assign cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read & ~jtag_uart_avalon_jtag_slave_waits_for_read; //jtag_uart_avalon_jtag_slave_writedata mux, which is an e_mux assign jtag_uart_avalon_jtag_slave_writedata = cpu_data_master_writedata; //master is always granted when requested assign cpu_data_master_granted_jtag_uart_avalon_jtag_slave = cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave; //cpu/data_master saved-grant jtag_uart/avalon_jtag_slave, which is an e_assign assign cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave; //allow new arb cycle for jtag_uart/avalon_jtag_slave, which is an e_assign assign jtag_uart_avalon_jtag_slave_allow_new_arb_cycle = 1; //placeholder chosen master assign jtag_uart_avalon_jtag_slave_grant_vector = 1; //placeholder vector of master qualified-requests assign jtag_uart_avalon_jtag_slave_master_qreq_vector = 1; //jtag_uart_avalon_jtag_slave_reset_n assignment, which is an e_assign assign jtag_uart_avalon_jtag_slave_reset_n = reset_n; assign jtag_uart_avalon_jtag_slave_chipselect = cpu_data_master_granted_jtag_uart_avalon_jtag_slave; //jtag_uart_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign assign jtag_uart_avalon_jtag_slave_firsttransfer = jtag_uart_avalon_jtag_slave_begins_xfer ? jtag_uart_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_avalon_jtag_slave_reg_firsttransfer; //jtag_uart_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign assign jtag_uart_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_avalon_jtag_slave_any_continuerequest); //jtag_uart_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) jtag_uart_avalon_jtag_slave_reg_firsttransfer <= 1'b1; else if (jtag_uart_avalon_jtag_slave_begins_xfer) jtag_uart_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_avalon_jtag_slave_unreg_firsttransfer; end //jtag_uart_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign assign jtag_uart_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_avalon_jtag_slave_begins_xfer; //~jtag_uart_avalon_jtag_slave_read_n assignment, which is an e_mux assign jtag_uart_avalon_jtag_slave_read_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read); //~jtag_uart_avalon_jtag_slave_write_n assignment, which is an e_mux assign jtag_uart_avalon_jtag_slave_write_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write); assign shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master = cpu_data_master_address_to_slave; //jtag_uart_avalon_jtag_slave_address mux, which is an e_mux assign jtag_uart_avalon_jtag_slave_address = shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master >> 2; //d1_jtag_uart_avalon_jtag_slave_end_xfer register, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d1_jtag_uart_avalon_jtag_slave_end_xfer <= 1; else if (1) d1_jtag_uart_avalon_jtag_slave_end_xfer <= jtag_uart_avalon_jtag_slave_end_xfer; end //jtag_uart_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux assign jtag_uart_avalon_jtag_slave_waits_for_read = jtag_uart_avalon_jtag_slave_in_a_read_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa; //jtag_uart_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign assign jtag_uart_avalon_jtag_slave_in_a_read_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read; //in_a_read_cycle assignment, which is an e_mux assign in_a_read_cycle = jtag_uart_avalon_jtag_slave_in_a_read_cycle; //jtag_uart_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux assign jtag_uart_avalon_jtag_slave_waits_for_write = jtag_uart_avalon_jtag_slave_in_a_write_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa; //jtag_uart_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign assign jtag_uart_avalon_jtag_slave_in_a_write_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write; //in_a_write_cycle assignment, which is an e_mux assign in_a_write_cycle = jtag_uart_avalon_jtag_slave_in_a_write_cycle; assign wait_for_jtag_uart_avalon_jtag_slave_counter = 0; //assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //jtag_uart/avalon_jtag_slave enable non-zero assertions, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) enable_nonzero_assertions <= 0; else if (1) enable_nonzero_assertions <= 1'b1; end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module onchip_mem_s1_arbitrator ( // inputs: clk, cpu_data_master_address_to_slave, cpu_data_master_byteenable, cpu_data_master_latency_counter, cpu_data_master_read, cpu_data_master_write, cpu_data_master_writedata, cpu_instruction_master_address_to_slave, cpu_instruction_master_latency_counter, cpu_instruction_master_read, onchip_mem_s1_readdata, reset_n, // outputs: cpu_data_master_granted_onchip_mem_s1, cpu_data_master_qualified_request_onchip_mem_s1, cpu_data_master_read_data_valid_onchip_mem_s1, cpu_data_master_requests_onchip_mem_s1, cpu_instruction_master_granted_onchip_mem_s1, cpu_instruction_master_qualified_request_onchip_mem_s1, cpu_instruction_master_read_data_valid_onchip_mem_s1, cpu_instruction_master_requests_onchip_mem_s1, d1_onchip_mem_s1_end_xfer, onchip_mem_s1_address, onchip_mem_s1_byteenable, onchip_mem_s1_chipselect, onchip_mem_s1_clken, onchip_mem_s1_readdata_from_sa, onchip_mem_s1_write, onchip_mem_s1_writedata ) /* synthesis auto_dissolve = "FALSE" */ ; output cpu_data_master_granted_onchip_mem_s1; output cpu_data_master_qualified_request_onchip_mem_s1; output cpu_data_master_read_data_valid_onchip_mem_s1; output cpu_data_master_requests_onchip_mem_s1; output cpu_instruction_master_granted_onchip_mem_s1; output cpu_instruction_master_qualified_request_onchip_mem_s1; output cpu_instruction_master_read_data_valid_onchip_mem_s1; output cpu_instruction_master_requests_onchip_mem_s1; output d1_onchip_mem_s1_end_xfer; output [ 12: 0] onchip_mem_s1_address; output [ 3: 0] onchip_mem_s1_byteenable; output onchip_mem_s1_chipselect; output onchip_mem_s1_clken; output [ 31: 0] onchip_mem_s1_readdata_from_sa; output onchip_mem_s1_write; output [ 31: 0] onchip_mem_s1_writedata; input clk; input [ 16: 0] cpu_data_master_address_to_slave; input [ 3: 0] cpu_data_master_byteenable; input cpu_data_master_latency_counter; input cpu_data_master_read; input cpu_data_master_write; input [ 31: 0] cpu_data_master_writedata; input [ 16: 0] cpu_instruction_master_address_to_slave; input cpu_instruction_master_latency_counter; input cpu_instruction_master_read; input [ 31: 0] onchip_mem_s1_readdata; input reset_n; wire cpu_data_master_arbiterlock; wire cpu_data_master_arbiterlock2; wire cpu_data_master_continuerequest; wire cpu_data_master_granted_onchip_mem_s1; wire cpu_data_master_qualified_request_onchip_mem_s1; wire cpu_data_master_read_data_valid_onchip_mem_s1; reg cpu_data_master_read_data_valid_onchip_mem_s1_shift_register; wire cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in; wire cpu_data_master_requests_onchip_mem_s1; wire cpu_data_master_saved_grant_onchip_mem_s1; wire cpu_instruction_master_arbiterlock; wire cpu_instruction_master_arbiterlock2; wire cpu_instruction_master_continuerequest; wire cpu_instruction_master_granted_onchip_mem_s1; wire cpu_instruction_master_qualified_request_onchip_mem_s1; wire cpu_instruction_master_read_data_valid_onchip_mem_s1; reg cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register; wire cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in; wire cpu_instruction_master_requests_onchip_mem_s1; wire cpu_instruction_master_saved_grant_onchip_mem_s1; reg d1_onchip_mem_s1_end_xfer; reg d1_reasons_to_wait; reg enable_nonzero_assertions; wire end_xfer_arb_share_counter_term_onchip_mem_s1; wire in_a_read_cycle; wire in_a_write_cycle; reg last_cycle_cpu_data_master_granted_slave_onchip_mem_s1; reg last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1; wire [ 12: 0] onchip_mem_s1_address; wire onchip_mem_s1_allgrants; wire onchip_mem_s1_allow_new_arb_cycle; wire onchip_mem_s1_any_bursting_master_saved_grant; wire onchip_mem_s1_any_continuerequest; reg [ 1: 0] onchip_mem_s1_arb_addend; wire onchip_mem_s1_arb_counter_enable; reg onchip_mem_s1_arb_share_counter; wire onchip_mem_s1_arb_share_counter_next_value; wire onchip_mem_s1_arb_share_set_values; wire [ 1: 0] onchip_mem_s1_arb_winner; wire onchip_mem_s1_arbitration_holdoff_internal; wire onchip_mem_s1_beginbursttransfer_internal; wire onchip_mem_s1_begins_xfer; wire [ 3: 0] onchip_mem_s1_byteenable; wire onchip_mem_s1_chipselect; wire [ 3: 0] onchip_mem_s1_chosen_master_double_vector; wire [ 1: 0] onchip_mem_s1_chosen_master_rot_left; wire onchip_mem_s1_clken; wire onchip_mem_s1_end_xfer; wire onchip_mem_s1_firsttransfer; wire [ 1: 0] onchip_mem_s1_grant_vector; wire onchip_mem_s1_in_a_read_cycle; wire onchip_mem_s1_in_a_write_cycle; wire [ 1: 0] onchip_mem_s1_master_qreq_vector; wire onchip_mem_s1_non_bursting_master_requests; wire [ 31: 0] onchip_mem_s1_readdata_from_sa; reg onchip_mem_s1_reg_firsttransfer; reg [ 1: 0] onchip_mem_s1_saved_chosen_master_vector; reg onchip_mem_s1_slavearbiterlockenable; wire onchip_mem_s1_slavearbiterlockenable2; wire onchip_mem_s1_unreg_firsttransfer; wire onchip_mem_s1_waits_for_read; wire onchip_mem_s1_waits_for_write; wire onchip_mem_s1_write; wire [ 31: 0] onchip_mem_s1_writedata; wire p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register; wire p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register; wire [ 16: 0] shifted_address_to_onchip_mem_s1_from_cpu_data_master; wire [ 16: 0] shifted_address_to_onchip_mem_s1_from_cpu_instruction_master; wire wait_for_onchip_mem_s1_counter; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d1_reasons_to_wait <= 0; else if (1) d1_reasons_to_wait <= ~onchip_mem_s1_end_xfer; end assign onchip_mem_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_onchip_mem_s1 | cpu_instruction_master_qualified_request_onchip_mem_s1)); //assign onchip_mem_s1_readdata_from_sa = onchip_mem_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign assign onchip_mem_s1_readdata_from_sa = onchip_mem_s1_readdata; assign cpu_data_master_requests_onchip_mem_s1 = ({cpu_data_master_address_to_slave[16 : 15] , 15'b0} == 17'h8000) & (cpu_data_master_read | cpu_data_master_write); //onchip_mem_s1_arb_share_counter set values, which is an e_mux assign onchip_mem_s1_arb_share_set_values = 1; //onchip_mem_s1_non_bursting_master_requests mux, which is an e_mux assign onchip_mem_s1_non_bursting_master_requests = cpu_data_master_requests_onchip_mem_s1 | cpu_instruction_master_requests_onchip_mem_s1 | cpu_data_master_requests_onchip_mem_s1 | cpu_instruction_master_requests_onchip_mem_s1; //onchip_mem_s1_any_bursting_master_saved_grant mux, which is an e_mux assign onchip_mem_s1_any_bursting_master_saved_grant = 0; //onchip_mem_s1_arb_share_counter_next_value assignment, which is an e_assign assign onchip_mem_s1_arb_share_counter_next_value = onchip_mem_s1_firsttransfer ? (onchip_mem_s1_arb_share_set_values - 1) : |onchip_mem_s1_arb_share_counter ? (onchip_mem_s1_arb_share_counter - 1) : 0; //onchip_mem_s1_allgrants all slave grants, which is an e_mux assign onchip_mem_s1_allgrants = |onchip_mem_s1_grant_vector | |onchip_mem_s1_grant_vector | |onchip_mem_s1_grant_vector | |onchip_mem_s1_grant_vector; //onchip_mem_s1_end_xfer assignment, which is an e_assign assign onchip_mem_s1_end_xfer = ~(onchip_mem_s1_waits_for_read | onchip_mem_s1_waits_for_write); //end_xfer_arb_share_counter_term_onchip_mem_s1 arb share counter enable term, which is an e_assign assign end_xfer_arb_share_counter_term_onchip_mem_s1 = onchip_mem_s1_end_xfer & (~onchip_mem_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle); //onchip_mem_s1_arb_share_counter arbitration counter enable, which is an e_assign assign onchip_mem_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_mem_s1 & onchip_mem_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_mem_s1 & ~onchip_mem_s1_non_bursting_master_requests); //onchip_mem_s1_arb_share_counter counter, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) onchip_mem_s1_arb_share_counter <= 0; else if (onchip_mem_s1_arb_counter_enable) onchip_mem_s1_arb_share_counter <= onchip_mem_s1_arb_share_counter_next_value; end //onchip_mem_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) onchip_mem_s1_slavearbiterlockenable <= 0; else if ((|onchip_mem_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_mem_s1) | (end_xfer_arb_share_counter_term_onchip_mem_s1 & ~onchip_mem_s1_non_bursting_master_requests)) onchip_mem_s1_slavearbiterlockenable <= |onchip_mem_s1_arb_share_counter_next_value; end //cpu/data_master onchip_mem/s1 arbiterlock, which is an e_assign assign cpu_data_master_arbiterlock = onchip_mem_s1_slavearbiterlockenable & cpu_data_master_continuerequest; //onchip_mem_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign assign onchip_mem_s1_slavearbiterlockenable2 = |onchip_mem_s1_arb_share_counter_next_value; //cpu/data_master onchip_mem/s1 arbiterlock2, which is an e_assign assign cpu_data_master_arbiterlock2 = onchip_mem_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest; //cpu/instruction_master onchip_mem/s1 arbiterlock, which is an e_assign assign cpu_instruction_master_arbiterlock = onchip_mem_s1_slavearbiterlockenable & cpu_instruction_master_continuerequest; //cpu/instruction_master onchip_mem/s1 arbiterlock2, which is an e_assign assign cpu_instruction_master_arbiterlock2 = onchip_mem_s1_slavearbiterlockenable2 & cpu_instruction_master_continuerequest; //cpu/instruction_master granted onchip_mem/s1 last time, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 <= 0; else if (1) last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 <= cpu_instruction_master_saved_grant_onchip_mem_s1 ? 1 : (onchip_mem_s1_arbitration_holdoff_internal | ~cpu_instruction_master_requests_onchip_mem_s1) ? 0 : last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1; end //cpu_instruction_master_continuerequest continued request, which is an e_mux assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_onchip_mem_s1 & cpu_instruction_master_requests_onchip_mem_s1; //onchip_mem_s1_any_continuerequest at least one master continues requesting, which is an e_mux assign onchip_mem_s1_any_continuerequest = cpu_instruction_master_continuerequest | cpu_data_master_continuerequest; assign cpu_data_master_qualified_request_onchip_mem_s1 = cpu_data_master_requests_onchip_mem_s1 & ~((cpu_data_master_read & ((1 < cpu_data_master_latency_counter))) | cpu_instruction_master_arbiterlock); //cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in mux for readlatency shift register, which is an e_mux assign cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_read & ~onchip_mem_s1_waits_for_read; //shift register p1 cpu_data_master_read_data_valid_onchip_mem_s1_shift_register in if flush, otherwise shift left, which is an e_mux assign p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register = {cpu_data_master_read_data_valid_onchip_mem_s1_shift_register, cpu_data_master_read_data_valid_onchip_mem_s1_shift_register_in}; //cpu_data_master_read_data_valid_onchip_mem_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_data_master_read_data_valid_onchip_mem_s1_shift_register <= 0; else if (1) cpu_data_master_read_data_valid_onchip_mem_s1_shift_register <= p1_cpu_data_master_read_data_valid_onchip_mem_s1_shift_register; end //local readdatavalid cpu_data_master_read_data_valid_onchip_mem_s1, which is an e_mux assign cpu_data_master_read_data_valid_onchip_mem_s1 = cpu_data_master_read_data_valid_onchip_mem_s1_shift_register; //onchip_mem_s1_writedata mux, which is an e_mux assign onchip_mem_s1_writedata = cpu_data_master_writedata; //mux onchip_mem_s1_clken, which is an e_mux assign onchip_mem_s1_clken = 1'b1; assign cpu_instruction_master_requests_onchip_mem_s1 = (({cpu_instruction_master_address_to_slave[16 : 15] , 15'b0} == 17'h8000) & (cpu_instruction_master_read)) & cpu_instruction_master_read; //cpu/data_master granted onchip_mem/s1 last time, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 <= 0; else if (1) last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 <= cpu_data_master_saved_grant_onchip_mem_s1 ? 1 : (onchip_mem_s1_arbitration_holdoff_internal | ~cpu_data_master_requests_onchip_mem_s1) ? 0 : last_cycle_cpu_data_master_granted_slave_onchip_mem_s1; end //cpu_data_master_continuerequest continued request, which is an e_mux assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_onchip_mem_s1 & cpu_data_master_requests_onchip_mem_s1; assign cpu_instruction_master_qualified_request_onchip_mem_s1 = cpu_instruction_master_requests_onchip_mem_s1 & ~((cpu_instruction_master_read & ((1 < cpu_instruction_master_latency_counter))) | cpu_data_master_arbiterlock); //cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in mux for readlatency shift register, which is an e_mux assign cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in = cpu_instruction_master_granted_onchip_mem_s1 & cpu_instruction_master_read & ~onchip_mem_s1_waits_for_read; //shift register p1 cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register in if flush, otherwise shift left, which is an e_mux assign p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register = {cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register, cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register_in}; //cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register <= 0; else if (1) cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register <= p1_cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register; end //local readdatavalid cpu_instruction_master_read_data_valid_onchip_mem_s1, which is an e_mux assign cpu_instruction_master_read_data_valid_onchip_mem_s1 = cpu_instruction_master_read_data_valid_onchip_mem_s1_shift_register; //allow new arb cycle for onchip_mem/s1, which is an e_assign assign onchip_mem_s1_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock; //cpu/instruction_master assignment into master qualified-requests vector for onchip_mem/s1, which is an e_assign assign onchip_mem_s1_master_qreq_vector[0] = cpu_instruction_master_qualified_request_onchip_mem_s1; //cpu/instruction_master grant onchip_mem/s1, which is an e_assign assign cpu_instruction_master_granted_onchip_mem_s1 = onchip_mem_s1_grant_vector[0]; //cpu/instruction_master saved-grant onchip_mem/s1, which is an e_assign assign cpu_instruction_master_saved_grant_onchip_mem_s1 = onchip_mem_s1_arb_winner[0] && cpu_instruction_master_requests_onchip_mem_s1; //cpu/data_master assignment into master qualified-requests vector for onchip_mem/s1, which is an e_assign assign onchip_mem_s1_master_qreq_vector[1] = cpu_data_master_qualified_request_onchip_mem_s1; //cpu/data_master grant onchip_mem/s1, which is an e_assign assign cpu_data_master_granted_onchip_mem_s1 = onchip_mem_s1_grant_vector[1]; //cpu/data_master saved-grant onchip_mem/s1, which is an e_assign assign cpu_data_master_saved_grant_onchip_mem_s1 = onchip_mem_s1_arb_winner[1] && cpu_data_master_requests_onchip_mem_s1; //onchip_mem/s1 chosen-master double-vector, which is an e_assign assign onchip_mem_s1_chosen_master_double_vector = {onchip_mem_s1_master_qreq_vector, onchip_mem_s1_master_qreq_vector} & ({~onchip_mem_s1_master_qreq_vector, ~onchip_mem_s1_master_qreq_vector} + onchip_mem_s1_arb_addend); //stable onehot encoding of arb winner assign onchip_mem_s1_arb_winner = (onchip_mem_s1_allow_new_arb_cycle & | onchip_mem_s1_grant_vector) ? onchip_mem_s1_grant_vector : onchip_mem_s1_saved_chosen_master_vector; //saved onchip_mem_s1_grant_vector, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) onchip_mem_s1_saved_chosen_master_vector <= 0; else if (onchip_mem_s1_allow_new_arb_cycle) onchip_mem_s1_saved_chosen_master_vector <= |onchip_mem_s1_grant_vector ? onchip_mem_s1_grant_vector : onchip_mem_s1_saved_chosen_master_vector; end //onehot encoding of chosen master assign onchip_mem_s1_grant_vector = {(onchip_mem_s1_chosen_master_double_vector[1] | onchip_mem_s1_chosen_master_double_vector[3]), (onchip_mem_s1_chosen_master_double_vector[0] | onchip_mem_s1_chosen_master_double_vector[2])}; //onchip_mem/s1 chosen master rotated left, which is an e_assign assign onchip_mem_s1_chosen_master_rot_left = (onchip_mem_s1_arb_winner << 1) ? (onchip_mem_s1_arb_winner << 1) : 1; //onchip_mem/s1's addend for next-master-grant always @(posedge clk or negedge reset_n) begin if (reset_n == 0) onchip_mem_s1_arb_addend <= 1; else if (|onchip_mem_s1_grant_vector) onchip_mem_s1_arb_addend <= onchip_mem_s1_end_xfer? onchip_mem_s1_chosen_master_rot_left : onchip_mem_s1_grant_vector; end assign onchip_mem_s1_chipselect = cpu_data_master_granted_onchip_mem_s1 | cpu_instruction_master_granted_onchip_mem_s1; //onchip_mem_s1_firsttransfer first transaction, which is an e_assign assign onchip_mem_s1_firsttransfer = onchip_mem_s1_begins_xfer ? onchip_mem_s1_unreg_firsttransfer : onchip_mem_s1_reg_firsttransfer; //onchip_mem_s1_unreg_firsttransfer first transaction, which is an e_assign assign onchip_mem_s1_unreg_firsttransfer = ~(onchip_mem_s1_slavearbiterlockenable & onchip_mem_s1_any_continuerequest); //onchip_mem_s1_reg_firsttransfer first transaction, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) onchip_mem_s1_reg_firsttransfer <= 1'b1; else if (onchip_mem_s1_begins_xfer) onchip_mem_s1_reg_firsttransfer <= onchip_mem_s1_unreg_firsttransfer; end //onchip_mem_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign assign onchip_mem_s1_beginbursttransfer_internal = onchip_mem_s1_begins_xfer; //onchip_mem_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign assign onchip_mem_s1_arbitration_holdoff_internal = onchip_mem_s1_begins_xfer & onchip_mem_s1_firsttransfer; //onchip_mem_s1_write assignment, which is an e_mux assign onchip_mem_s1_write = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_write; assign shifted_address_to_onchip_mem_s1_from_cpu_data_master = cpu_data_master_address_to_slave; //onchip_mem_s1_address mux, which is an e_mux assign onchip_mem_s1_address = (cpu_data_master_granted_onchip_mem_s1)? (shifted_address_to_onchip_mem_s1_from_cpu_data_master >> 2) : (shifted_address_to_onchip_mem_s1_from_cpu_instruction_master >> 2); assign shifted_address_to_onchip_mem_s1_from_cpu_instruction_master = cpu_instruction_master_address_to_slave; //d1_onchip_mem_s1_end_xfer register, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d1_onchip_mem_s1_end_xfer <= 1; else if (1) d1_onchip_mem_s1_end_xfer <= onchip_mem_s1_end_xfer; end //onchip_mem_s1_waits_for_read in a cycle, which is an e_mux assign onchip_mem_s1_waits_for_read = onchip_mem_s1_in_a_read_cycle & 0; //onchip_mem_s1_in_a_read_cycle assignment, which is an e_assign assign onchip_mem_s1_in_a_read_cycle = (cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_onchip_mem_s1 & cpu_instruction_master_read); //in_a_read_cycle assignment, which is an e_mux assign in_a_read_cycle = onchip_mem_s1_in_a_read_cycle; //onchip_mem_s1_waits_for_write in a cycle, which is an e_mux assign onchip_mem_s1_waits_for_write = onchip_mem_s1_in_a_write_cycle & 0; //onchip_mem_s1_in_a_write_cycle assignment, which is an e_assign assign onchip_mem_s1_in_a_write_cycle = cpu_data_master_granted_onchip_mem_s1 & cpu_data_master_write; //in_a_write_cycle assignment, which is an e_mux assign in_a_write_cycle = onchip_mem_s1_in_a_write_cycle; assign wait_for_onchip_mem_s1_counter = 0; //onchip_mem_s1_byteenable byte enable port mux, which is an e_mux assign onchip_mem_s1_byteenable = (cpu_data_master_granted_onchip_mem_s1)? cpu_data_master_byteenable : -1; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //onchip_mem/s1 enable non-zero assertions, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) enable_nonzero_assertions <= 0; else if (1) enable_nonzero_assertions <= 1'b1; end //grant signals are active simultaneously, which is an e_process always @(posedge clk) begin if (cpu_data_master_granted_onchip_mem_s1 + cpu_instruction_master_granted_onchip_mem_s1 > 1) begin $write("%0d ns: > 1 of grant signals are active simultaneously", $time); $stop; end end //saved_grant signals are active simultaneously, which is an e_process always @(posedge clk) begin if (cpu_data_master_saved_grant_onchip_mem_s1 + cpu_instruction_master_saved_grant_onchip_mem_s1 > 1) begin $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time); $stop; end end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module pio_s1_arbitrator ( // inputs: clk, cpu_data_master_address_to_slave, cpu_data_master_latency_counter, cpu_data_master_read, cpu_data_master_write, cpu_data_master_writedata, pio_s1_readdata, reset_n, // outputs: cpu_data_master_granted_pio_s1, cpu_data_master_qualified_request_pio_s1, cpu_data_master_read_data_valid_pio_s1, cpu_data_master_requests_pio_s1, d1_pio_s1_end_xfer, pio_s1_address, pio_s1_chipselect, pio_s1_readdata_from_sa, pio_s1_reset_n, pio_s1_write_n, pio_s1_writedata ) /* synthesis auto_dissolve = "FALSE" */ ; output cpu_data_master_granted_pio_s1; output cpu_data_master_qualified_request_pio_s1; output cpu_data_master_read_data_valid_pio_s1; output cpu_data_master_requests_pio_s1; output d1_pio_s1_end_xfer; output [ 1: 0] pio_s1_address; output pio_s1_chipselect; output [ 31: 0] pio_s1_readdata_from_sa; output pio_s1_reset_n; output pio_s1_write_n; output [ 31: 0] pio_s1_writedata; input clk; input [ 16: 0] cpu_data_master_address_to_slave; input cpu_data_master_latency_counter; input cpu_data_master_read; input cpu_data_master_write; input [ 31: 0] cpu_data_master_writedata; input [ 31: 0] pio_s1_readdata; input reset_n; wire cpu_data_master_arbiterlock; wire cpu_data_master_arbiterlock2; wire cpu_data_master_continuerequest; wire cpu_data_master_granted_pio_s1; wire cpu_data_master_qualified_request_pio_s1; wire cpu_data_master_read_data_valid_pio_s1; wire cpu_data_master_requests_pio_s1; wire cpu_data_master_saved_grant_pio_s1; reg d1_pio_s1_end_xfer; reg d1_reasons_to_wait; reg enable_nonzero_assertions; wire end_xfer_arb_share_counter_term_pio_s1; wire in_a_read_cycle; wire in_a_write_cycle; wire [ 1: 0] pio_s1_address; wire pio_s1_allgrants; wire pio_s1_allow_new_arb_cycle; wire pio_s1_any_bursting_master_saved_grant; wire pio_s1_any_continuerequest; wire pio_s1_arb_counter_enable; reg pio_s1_arb_share_counter; wire pio_s1_arb_share_counter_next_value; wire pio_s1_arb_share_set_values; wire pio_s1_beginbursttransfer_internal; wire pio_s1_begins_xfer; wire pio_s1_chipselect; wire pio_s1_end_xfer; wire pio_s1_firsttransfer; wire pio_s1_grant_vector; wire pio_s1_in_a_read_cycle; wire pio_s1_in_a_write_cycle; wire pio_s1_master_qreq_vector; wire pio_s1_non_bursting_master_requests; wire [ 31: 0] pio_s1_readdata_from_sa; reg pio_s1_reg_firsttransfer; wire pio_s1_reset_n; reg pio_s1_slavearbiterlockenable; wire pio_s1_slavearbiterlockenable2; wire pio_s1_unreg_firsttransfer; wire pio_s1_waits_for_read; wire pio_s1_waits_for_write; wire pio_s1_write_n; wire [ 31: 0] pio_s1_writedata; wire [ 16: 0] shifted_address_to_pio_s1_from_cpu_data_master; wire wait_for_pio_s1_counter; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d1_reasons_to_wait <= 0; else if (1) d1_reasons_to_wait <= ~pio_s1_end_xfer; end assign pio_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_pio_s1)); //assign pio_s1_readdata_from_sa = pio_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign assign pio_s1_readdata_from_sa = pio_s1_readdata; assign cpu_data_master_requests_pio_s1 = ({cpu_data_master_address_to_slave[16 : 4] , 4'b0} == 17'h11000) & (cpu_data_master_read | cpu_data_master_write); //pio_s1_arb_share_counter set values, which is an e_mux assign pio_s1_arb_share_set_values = 1; //pio_s1_non_bursting_master_requests mux, which is an e_mux assign pio_s1_non_bursting_master_requests = cpu_data_master_requests_pio_s1; //pio_s1_any_bursting_master_saved_grant mux, which is an e_mux assign pio_s1_any_bursting_master_saved_grant = 0; //pio_s1_arb_share_counter_next_value assignment, which is an e_assign assign pio_s1_arb_share_counter_next_value = pio_s1_firsttransfer ? (pio_s1_arb_share_set_values - 1) : |pio_s1_arb_share_counter ? (pio_s1_arb_share_counter - 1) : 0; //pio_s1_allgrants all slave grants, which is an e_mux assign pio_s1_allgrants = |pio_s1_grant_vector; //pio_s1_end_xfer assignment, which is an e_assign assign pio_s1_end_xfer = ~(pio_s1_waits_for_read | pio_s1_waits_for_write); //end_xfer_arb_share_counter_term_pio_s1 arb share counter enable term, which is an e_assign assign end_xfer_arb_share_counter_term_pio_s1 = pio_s1_end_xfer & (~pio_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle); //pio_s1_arb_share_counter arbitration counter enable, which is an e_assign assign pio_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_pio_s1 & pio_s1_allgrants) | (end_xfer_arb_share_counter_term_pio_s1 & ~pio_s1_non_bursting_master_requests); //pio_s1_arb_share_counter counter, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) pio_s1_arb_share_counter <= 0; else if (pio_s1_arb_counter_enable) pio_s1_arb_share_counter <= pio_s1_arb_share_counter_next_value; end //pio_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) pio_s1_slavearbiterlockenable <= 0; else if ((|pio_s1_master_qreq_vector & end_xfer_arb_share_counter_term_pio_s1) | (end_xfer_arb_share_counter_term_pio_s1 & ~pio_s1_non_bursting_master_requests)) pio_s1_slavearbiterlockenable <= |pio_s1_arb_share_counter_next_value; end //cpu/data_master pio/s1 arbiterlock, which is an e_assign assign cpu_data_master_arbiterlock = pio_s1_slavearbiterlockenable & cpu_data_master_continuerequest; //pio_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign assign pio_s1_slavearbiterlockenable2 = |pio_s1_arb_share_counter_next_value; //cpu/data_master pio/s1 arbiterlock2, which is an e_assign assign cpu_data_master_arbiterlock2 = pio_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest; //pio_s1_any_continuerequest at least one master continues requesting, which is an e_assign assign pio_s1_any_continuerequest = 1; //cpu_data_master_continuerequest continued request, which is an e_assign assign cpu_data_master_continuerequest = 1; assign cpu_data_master_qualified_request_pio_s1 = cpu_data_master_requests_pio_s1 & ~((cpu_data_master_read & ((cpu_data_master_latency_counter != 0)))); //local readdatavalid cpu_data_master_read_data_valid_pio_s1, which is an e_mux assign cpu_data_master_read_data_valid_pio_s1 = cpu_data_master_granted_pio_s1 & cpu_data_master_read & ~pio_s1_waits_for_read; //pio_s1_writedata mux, which is an e_mux assign pio_s1_writedata = cpu_data_master_writedata; //master is always granted when requested assign cpu_data_master_granted_pio_s1 = cpu_data_master_qualified_request_pio_s1; //cpu/data_master saved-grant pio/s1, which is an e_assign assign cpu_data_master_saved_grant_pio_s1 = cpu_data_master_requests_pio_s1; //allow new arb cycle for pio/s1, which is an e_assign assign pio_s1_allow_new_arb_cycle = 1; //placeholder chosen master assign pio_s1_grant_vector = 1; //placeholder vector of master qualified-requests assign pio_s1_master_qreq_vector = 1; //pio_s1_reset_n assignment, which is an e_assign assign pio_s1_reset_n = reset_n; assign pio_s1_chipselect = cpu_data_master_granted_pio_s1; //pio_s1_firsttransfer first transaction, which is an e_assign assign pio_s1_firsttransfer = pio_s1_begins_xfer ? pio_s1_unreg_firsttransfer : pio_s1_reg_firsttransfer; //pio_s1_unreg_firsttransfer first transaction, which is an e_assign assign pio_s1_unreg_firsttransfer = ~(pio_s1_slavearbiterlockenable & pio_s1_any_continuerequest); //pio_s1_reg_firsttransfer first transaction, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) pio_s1_reg_firsttransfer <= 1'b1; else if (pio_s1_begins_xfer) pio_s1_reg_firsttransfer <= pio_s1_unreg_firsttransfer; end //pio_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign assign pio_s1_beginbursttransfer_internal = pio_s1_begins_xfer; //~pio_s1_write_n assignment, which is an e_mux assign pio_s1_write_n = ~(cpu_data_master_granted_pio_s1 & cpu_data_master_write); assign shifted_address_to_pio_s1_from_cpu_data_master = cpu_data_master_address_to_slave; //pio_s1_address mux, which is an e_mux assign pio_s1_address = shifted_address_to_pio_s1_from_cpu_data_master >> 2; //d1_pio_s1_end_xfer register, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) d1_pio_s1_end_xfer <= 1; else if (1) d1_pio_s1_end_xfer <= pio_s1_end_xfer; end //pio_s1_waits_for_read in a cycle, which is an e_mux assign pio_s1_waits_for_read = pio_s1_in_a_read_cycle & pio_s1_begins_xfer; //pio_s1_in_a_read_cycle assignment, which is an e_assign assign pio_s1_in_a_read_cycle = cpu_data_master_granted_pio_s1 & cpu_data_master_read; //in_a_read_cycle assignment, which is an e_mux assign in_a_read_cycle = pio_s1_in_a_read_cycle; //pio_s1_waits_for_write in a cycle, which is an e_mux assign pio_s1_waits_for_write = pio_s1_in_a_write_cycle & 0; //pio_s1_in_a_write_cycle assignment, which is an e_assign assign pio_s1_in_a_write_cycle = cpu_data_master_granted_pio_s1 & cpu_data_master_write; //in_a_write_cycle assignment, which is an e_mux assign in_a_write_cycle = pio_s1_in_a_write_cycle; assign wait_for_pio_s1_counter = 0; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //pio/s1 enable non-zero assertions, which is an e_register always @(posedge clk or negedge reset_n) begin if (reset_n == 0) enable_nonzero_assertions <= 0; else if (1) enable_nonzero_assertions <= 1'b1; end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu1_reset_clk_domain_synch_module ( // inputs: clk, data_in, reset_n, // outputs: data_out ) ; output data_out; input clk; input data_in; input reset_n; reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */; reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) data_in_d1 <= 0; else if (1) data_in_d1 <= data_in; end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) data_out <= 0; else if (1) data_out <= data_in_d1; end endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu1 ( // 1) global signals: clk, reset_n, // the_pio in_port_to_the_pio, out_port_from_the_pio ) ; output [ 31: 0] out_port_from_the_pio; input clk; input [ 31: 0] in_port_to_the_pio; input reset_n; wire clk_reset_n; wire [ 16: 0] cpu_data_master_address; wire [ 16: 0] cpu_data_master_address_to_slave; wire [ 3: 0] cpu_data_master_byteenable; wire cpu_data_master_debugaccess; wire cpu_data_master_granted_cpu_jtag_debug_module; wire cpu_data_master_granted_jtag_uart_avalon_jtag_slave; wire cpu_data_master_granted_onchip_mem_s1; wire cpu_data_master_granted_pio_s1; wire [ 31: 0] cpu_data_master_irq; wire cpu_data_master_latency_counter; wire cpu_data_master_qualified_request_cpu_jtag_debug_module; wire cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave; wire cpu_data_master_qualified_request_onchip_mem_s1; wire cpu_data_master_qualified_request_pio_s1; wire cpu_data_master_read; wire cpu_data_master_read_data_valid_cpu_jtag_debug_module; wire cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave; wire cpu_data_master_read_data_valid_onchip_mem_s1; wire cpu_data_master_read_data_valid_pio_s1; wire [ 31: 0] cpu_data_master_readdata; wire cpu_data_master_readdatavalid; wire cpu_data_master_requests_cpu_jtag_debug_module; wire cpu_data_master_requests_jtag_uart_avalon_jtag_slave; wire cpu_data_master_requests_onchip_mem_s1; wire cpu_data_master_requests_pio_s1; wire cpu_data_master_waitrequest; wire cpu_data_master_write; wire [ 31: 0] cpu_data_master_writedata; wire [ 16: 0] cpu_instruction_master_address; wire [ 16: 0] cpu_instruction_master_address_to_slave; wire cpu_instruction_master_granted_cpu_jtag_debug_module; wire cpu_instruction_master_granted_onchip_mem_s1; wire cpu_instruction_master_latency_counter; wire cpu_instruction_master_qualified_request_cpu_jtag_debug_module; wire cpu_instruction_master_qualified_request_onchip_mem_s1; wire cpu_instruction_master_read; wire cpu_instruction_master_read_data_valid_cpu_jtag_debug_module; wire cpu_instruction_master_read_data_valid_onchip_mem_s1; wire [ 31: 0] cpu_instruction_master_readdata; wire cpu_instruction_master_readdatavalid; wire cpu_instruction_master_requests_cpu_jtag_debug_module; wire cpu_instruction_master_requests_onchip_mem_s1; wire cpu_instruction_master_waitrequest; wire [ 8: 0] cpu_jtag_debug_module_address; wire cpu_jtag_debug_module_begintransfer; wire [ 3: 0] cpu_jtag_debug_module_byteenable; wire cpu_jtag_debug_module_chipselect; wire cpu_jtag_debug_module_debugaccess; wire [ 31: 0] cpu_jtag_debug_module_readdata; wire [ 31: 0] cpu_jtag_debug_module_readdata_from_sa; wire cpu_jtag_debug_module_reset; wire cpu_jtag_debug_module_reset_n; wire cpu_jtag_debug_module_resetrequest; wire cpu_jtag_debug_module_resetrequest_from_sa; wire cpu_jtag_debug_module_write; wire [ 31: 0] cpu_jtag_debug_module_writedata; wire d1_cpu_jtag_debug_module_end_xfer; wire d1_jtag_uart_avalon_jtag_slave_end_xfer; wire d1_onchip_mem_s1_end_xfer; wire d1_pio_s1_end_xfer; wire jtag_uart_avalon_jtag_slave_address; wire jtag_uart_avalon_jtag_slave_chipselect; wire jtag_uart_avalon_jtag_slave_dataavailable; wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa; wire jtag_uart_avalon_jtag_slave_irq; wire jtag_uart_avalon_jtag_slave_irq_from_sa; wire jtag_uart_avalon_jtag_slave_read_n; wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata; wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa; wire jtag_uart_avalon_jtag_slave_readyfordata; wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa; wire jtag_uart_avalon_jtag_slave_reset_n; wire jtag_uart_avalon_jtag_slave_waitrequest; wire jtag_uart_avalon_jtag_slave_waitrequest_from_sa; wire jtag_uart_avalon_jtag_slave_write_n; wire [ 31: 0] jtag_uart_avalon_jtag_slave_writedata; wire [ 12: 0] onchip_mem_s1_address; wire [ 3: 0] onchip_mem_s1_byteenable; wire onchip_mem_s1_chipselect; wire onchip_mem_s1_clken; wire [ 31: 0] onchip_mem_s1_readdata; wire [ 31: 0] onchip_mem_s1_readdata_from_sa; wire onchip_mem_s1_write; wire [ 31: 0] onchip_mem_s1_writedata; wire [ 31: 0] out_port_from_the_pio; wire [ 1: 0] pio_s1_address; wire pio_s1_chipselect; wire [ 31: 0] pio_s1_readdata; wire [ 31: 0] pio_s1_readdata_from_sa; wire pio_s1_reset_n; wire pio_s1_write_n; wire [ 31: 0] pio_s1_writedata; wire reset_n_sources; cpu_jtag_debug_module_arbitrator the_cpu_jtag_debug_module ( .clk (clk), .cpu_data_master_address_to_slave (cpu_data_master_address_to_slave), .cpu_data_master_byteenable (cpu_data_master_byteenable), .cpu_data_master_debugaccess (cpu_data_master_debugaccess), .cpu_data_master_granted_cpu_jtag_debug_module (cpu_data_master_granted_cpu_jtag_debug_module), .cpu_data_master_latency_counter (cpu_data_master_latency_counter), .cpu_data_master_qualified_request_cpu_jtag_debug_module (cpu_data_master_qualified_request_cpu_jtag_debug_module), .cpu_data_master_read (cpu_data_master_read), .cpu_data_master_read_data_valid_cpu_jtag_debug_module (cpu_data_master_read_data_valid_cpu_jtag_debug_module), .cpu_data_master_requests_cpu_jtag_debug_module (cpu_data_master_requests_cpu_jtag_debug_module), .cpu_data_master_write (cpu_data_master_write), .cpu_data_master_writedata (cpu_data_master_writedata), .cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave), .cpu_instruction_master_granted_cpu_jtag_debug_module (cpu_instruction_master_granted_cpu_jtag_debug_module), .cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter), .cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module), .cpu_instruction_master_read (cpu_instruction_master_read), .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module), .cpu_instruction_master_requests_cpu_jtag_debug_module (cpu_instruction_master_requests_cpu_jtag_debug_module), .cpu_jtag_debug_module_address (cpu_jtag_debug_module_address), .cpu_jtag_debug_module_begintransfer (cpu_jtag_debug_module_begintransfer), .cpu_jtag_debug_module_byteenable (cpu_jtag_debug_module_byteenable), .cpu_jtag_debug_module_chipselect (cpu_jtag_debug_module_chipselect), .cpu_jtag_debug_module_debugaccess (cpu_jtag_debug_module_debugaccess), .cpu_jtag_debug_module_readdata (cpu_jtag_debug_module_readdata), .cpu_jtag_debug_module_readdata_from_sa (cpu_jtag_debug_module_readdata_from_sa), .cpu_jtag_debug_module_reset (cpu_jtag_debug_module_reset), .cpu_jtag_debug_module_reset_n (cpu_jtag_debug_module_reset_n), .cpu_jtag_debug_module_resetrequest (cpu_jtag_debug_module_resetrequest), .cpu_jtag_debug_module_resetrequest_from_sa (cpu_jtag_debug_module_resetrequest_from_sa), .cpu_jtag_debug_module_write (cpu_jtag_debug_module_write), .cpu_jtag_debug_module_writedata (cpu_jtag_debug_module_writedata), .d1_cpu_jtag_debug_module_end_xfer (d1_cpu_jtag_debug_module_end_xfer), .reset_n (clk_reset_n) ); cpu_data_master_arbitrator the_cpu_data_master ( .clk (clk), .cpu_data_master_address (cpu_data_master_address), .cpu_data_master_address_to_slave (cpu_data_master_address_to_slave), .cpu_data_master_debugaccess (cpu_data_master_debugaccess), .cpu_data_master_granted_cpu_jtag_debug_module (cpu_data_master_granted_cpu_jtag_debug_module), .cpu_data_master_granted_jtag_uart_avalon_jtag_slave (cpu_data_master_granted_jtag_uart_avalon_jtag_slave), .cpu_data_master_granted_onchip_mem_s1 (cpu_data_master_granted_onchip_mem_s1), .cpu_data_master_granted_pio_s1 (cpu_data_master_granted_pio_s1), .cpu_data_master_irq (cpu_data_master_irq), .cpu_data_master_latency_counter (cpu_data_master_latency_counter), .cpu_data_master_qualified_request_cpu_jtag_debug_module (cpu_data_master_qualified_request_cpu_jtag_debug_module), .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave), .cpu_data_master_qualified_request_onchip_mem_s1 (cpu_data_master_qualified_request_onchip_mem_s1), .cpu_data_master_qualified_request_pio_s1 (cpu_data_master_qualified_request_pio_s1), .cpu_data_master_read (cpu_data_master_read), .cpu_data_master_read_data_valid_cpu_jtag_debug_module (cpu_data_master_read_data_valid_cpu_jtag_debug_module), .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave), .cpu_data_master_read_data_valid_onchip_mem_s1 (cpu_data_master_read_data_valid_onchip_mem_s1), .cpu_data_master_read_data_valid_pio_s1 (cpu_data_master_read_data_valid_pio_s1), .cpu_data_master_readdata (cpu_data_master_readdata), .cpu_data_master_readdatavalid (cpu_data_master_readdatavalid), .cpu_data_master_requests_cpu_jtag_debug_module (cpu_data_master_requests_cpu_jtag_debug_module), .cpu_data_master_requests_jtag_uart_avalon_jtag_slave (cpu_data_master_requests_jtag_uart_avalon_jtag_slave), .cpu_data_master_requests_onchip_mem_s1 (cpu_data_master_requests_onchip_mem_s1), .cpu_data_master_requests_pio_s1 (cpu_data_master_requests_pio_s1), .cpu_data_master_waitrequest (cpu_data_master_waitrequest), .cpu_data_master_write (cpu_data_master_write), .cpu_data_master_writedata (cpu_data_master_writedata), .cpu_jtag_debug_module_readdata_from_sa (cpu_jtag_debug_module_readdata_from_sa), .d1_cpu_jtag_debug_module_end_xfer (d1_cpu_jtag_debug_module_end_xfer), .d1_jtag_uart_avalon_jtag_slave_end_xfer (d1_jtag_uart_avalon_jtag_slave_end_xfer), .d1_onchip_mem_s1_end_xfer (d1_onchip_mem_s1_end_xfer), .d1_pio_s1_end_xfer (d1_pio_s1_end_xfer), .jtag_uart_avalon_jtag_slave_irq_from_sa (jtag_uart_avalon_jtag_slave_irq_from_sa), .jtag_uart_avalon_jtag_slave_readdata_from_sa (jtag_uart_avalon_jtag_slave_readdata_from_sa), .jtag_uart_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_avalon_jtag_slave_waitrequest_from_sa), .onchip_mem_s1_readdata_from_sa (onchip_mem_s1_readdata_from_sa), .pio_s1_readdata_from_sa (pio_s1_readdata_from_sa), .reset_n (clk_reset_n) ); cpu_instruction_master_arbitrator the_cpu_instruction_master ( .clk (clk), .cpu_instruction_master_address (cpu_instruction_master_address), .cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave), .cpu_instruction_master_granted_cpu_jtag_debug_module (cpu_instruction_master_granted_cpu_jtag_debug_module), .cpu_instruction_master_granted_onchip_mem_s1 (cpu_instruction_master_granted_onchip_mem_s1), .cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter), .cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module), .cpu_instruction_master_qualified_request_onchip_mem_s1 (cpu_instruction_master_qualified_request_onchip_mem_s1), .cpu_instruction_master_read (cpu_instruction_master_read), .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module), .cpu_instruction_master_read_data_valid_onchip_mem_s1 (cpu_instruction_master_read_data_valid_onchip_mem_s1), .cpu_instruction_master_readdata (cpu_instruction_master_readdata), .cpu_instruction_master_readdatavalid (cpu_instruction_master_readdatavalid), .cpu_instruction_master_requests_cpu_jtag_debug_module (cpu_instruction_master_requests_cpu_jtag_debug_module), .cpu_instruction_master_requests_onchip_mem_s1 (cpu_instruction_master_requests_onchip_mem_s1), .cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), .cpu_jtag_debug_module_readdata_from_sa (cpu_jtag_debug_module_readdata_from_sa), .d1_cpu_jtag_debug_module_end_xfer (d1_cpu_jtag_debug_module_end_xfer), .d1_onchip_mem_s1_end_xfer (d1_onchip_mem_s1_end_xfer), .onchip_mem_s1_readdata_from_sa (onchip_mem_s1_readdata_from_sa), .reset_n (clk_reset_n) ); cpu the_cpu ( .clk (clk), .d_address (cpu_data_master_address), .d_byteenable (cpu_data_master_byteenable), .d_irq (cpu_data_master_irq), .d_read (cpu_data_master_read), .d_readdata (cpu_data_master_readdata), .d_readdatavalid (cpu_data_master_readdatavalid), .d_waitrequest (cpu_data_master_waitrequest), .d_write (cpu_data_master_write), .d_writedata (cpu_data_master_writedata), .i_address (cpu_instruction_master_address), .i_read (cpu_instruction_master_read), .i_readdata (cpu_instruction_master_readdata), .i_readdatavalid (cpu_instruction_master_readdatavalid), .i_waitrequest (cpu_instruction_master_waitrequest), .jtag_debug_module_address (cpu_jtag_debug_module_address), .jtag_debug_module_begintransfer (cpu_jtag_debug_module_begintransfer), .jtag_debug_module_byteenable (cpu_jtag_debug_module_byteenable), .jtag_debug_module_clk (clk), .jtag_debug_module_debugaccess (cpu_jtag_debug_module_debugaccess), .jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), .jtag_debug_module_readdata (cpu_jtag_debug_module_readdata), .jtag_debug_module_reset (cpu_jtag_debug_module_reset), .jtag_debug_module_resetrequest (cpu_jtag_debug_module_resetrequest), .jtag_debug_module_select (cpu_jtag_debug_module_chipselect), .jtag_debug_module_write (cpu_jtag_debug_module_write), .jtag_debug_module_writedata (cpu_jtag_debug_module_writedata), .reset_n (cpu_jtag_debug_module_reset_n) ); jtag_uart_avalon_jtag_slave_arbitrator the_jtag_uart_avalon_jtag_slave ( .clk (clk), .cpu_data_master_address_to_slave (cpu_data_master_address_to_slave), .cpu_data_master_granted_jtag_uart_avalon_jtag_slave (cpu_data_master_granted_jtag_uart_avalon_jtag_slave), .cpu_data_master_latency_counter (cpu_data_master_latency_counter), .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave), .cpu_data_master_read (cpu_data_master_read), .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave), .cpu_data_master_requests_jtag_uart_avalon_jtag_slave (cpu_data_master_requests_jtag_uart_avalon_jtag_slave), .cpu_data_master_write (cpu_data_master_write), .cpu_data_master_writedata (cpu_data_master_writedata), .d1_jtag_uart_avalon_jtag_slave_end_xfer (d1_jtag_uart_avalon_jtag_slave_end_xfer), .jtag_uart_avalon_jtag_slave_address (jtag_uart_avalon_jtag_slave_address), .jtag_uart_avalon_jtag_slave_chipselect (jtag_uart_avalon_jtag_slave_chipselect), .jtag_uart_avalon_jtag_slave_dataavailable (jtag_uart_avalon_jtag_slave_dataavailable), .jtag_uart_avalon_jtag_slave_dataavailable_from_sa (jtag_uart_avalon_jtag_slave_dataavailable_from_sa), .jtag_uart_avalon_jtag_slave_irq (jtag_uart_avalon_jtag_slave_irq), .jtag_uart_avalon_jtag_slave_irq_from_sa (jtag_uart_avalon_jtag_slave_irq_from_sa), .jtag_uart_avalon_jtag_slave_read_n (jtag_uart_avalon_jtag_slave_read_n), .jtag_uart_avalon_jtag_slave_readdata (jtag_uart_avalon_jtag_slave_readdata), .jtag_uart_avalon_jtag_slave_readdata_from_sa (jtag_uart_avalon_jtag_slave_readdata_from_sa), .jtag_uart_avalon_jtag_slave_readyfordata (jtag_uart_avalon_jtag_slave_readyfordata), .jtag_uart_avalon_jtag_slave_readyfordata_from_sa (jtag_uart_avalon_jtag_slave_readyfordata_from_sa), .jtag_uart_avalon_jtag_slave_reset_n (jtag_uart_avalon_jtag_slave_reset_n), .jtag_uart_avalon_jtag_slave_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), .jtag_uart_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_avalon_jtag_slave_waitrequest_from_sa), .jtag_uart_avalon_jtag_slave_write_n (jtag_uart_avalon_jtag_slave_write_n), .jtag_uart_avalon_jtag_slave_writedata (jtag_uart_avalon_jtag_slave_writedata), .reset_n (clk_reset_n) ); jtag_uart the_jtag_uart ( .av_address (jtag_uart_avalon_jtag_slave_address), .av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), .av_irq (jtag_uart_avalon_jtag_slave_irq), .av_read_n (jtag_uart_avalon_jtag_slave_read_n), .av_readdata (jtag_uart_avalon_jtag_slave_readdata), .av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), .av_write_n (jtag_uart_avalon_jtag_slave_write_n), .av_writedata (jtag_uart_avalon_jtag_slave_writedata), .clk (clk), .dataavailable (jtag_uart_avalon_jtag_slave_dataavailable), .readyfordata (jtag_uart_avalon_jtag_slave_readyfordata), .rst_n (jtag_uart_avalon_jtag_slave_reset_n) ); onchip_mem_s1_arbitrator the_onchip_mem_s1 ( .clk (clk), .cpu_data_master_address_to_slave (cpu_data_master_address_to_slave), .cpu_data_master_byteenable (cpu_data_master_byteenable), .cpu_data_master_granted_onchip_mem_s1 (cpu_data_master_granted_onchip_mem_s1), .cpu_data_master_latency_counter (cpu_data_master_latency_counter), .cpu_data_master_qualified_request_onchip_mem_s1 (cpu_data_master_qualified_request_onchip_mem_s1), .cpu_data_master_read (cpu_data_master_read), .cpu_data_master_read_data_valid_onchip_mem_s1 (cpu_data_master_read_data_valid_onchip_mem_s1), .cpu_data_master_requests_onchip_mem_s1 (cpu_data_master_requests_onchip_mem_s1), .cpu_data_master_write (cpu_data_master_write), .cpu_data_master_writedata (cpu_data_master_writedata), .cpu_instruction_master_address_to_slave (cpu_instruction_master_address_to_slave), .cpu_instruction_master_granted_onchip_mem_s1 (cpu_instruction_master_granted_onchip_mem_s1), .cpu_instruction_master_latency_counter (cpu_instruction_master_latency_counter), .cpu_instruction_master_qualified_request_onchip_mem_s1 (cpu_instruction_master_qualified_request_onchip_mem_s1), .cpu_instruction_master_read (cpu_instruction_master_read), .cpu_instruction_master_read_data_valid_onchip_mem_s1 (cpu_instruction_master_read_data_valid_onchip_mem_s1), .cpu_instruction_master_requests_onchip_mem_s1 (cpu_instruction_master_requests_onchip_mem_s1), .d1_onchip_mem_s1_end_xfer (d1_onchip_mem_s1_end_xfer), .onchip_mem_s1_address (onchip_mem_s1_address), .onchip_mem_s1_byteenable (onchip_mem_s1_byteenable), .onchip_mem_s1_chipselect (onchip_mem_s1_chipselect), .onchip_mem_s1_clken (onchip_mem_s1_clken), .onchip_mem_s1_readdata (onchip_mem_s1_readdata), .onchip_mem_s1_readdata_from_sa (onchip_mem_s1_readdata_from_sa), .onchip_mem_s1_write (onchip_mem_s1_write), .onchip_mem_s1_writedata (onchip_mem_s1_writedata), .reset_n (clk_reset_n) ); onchip_mem the_onchip_mem ( .address (onchip_mem_s1_address), .byteenable (onchip_mem_s1_byteenable), .chipselect (onchip_mem_s1_chipselect), .clk (clk), .clken (onchip_mem_s1_clken), .readdata (onchip_mem_s1_readdata), .write (onchip_mem_s1_write), .writedata (onchip_mem_s1_writedata) ); pio_s1_arbitrator the_pio_s1 ( .clk (clk), .cpu_data_master_address_to_slave (cpu_data_master_address_to_slave), .cpu_data_master_granted_pio_s1 (cpu_data_master_granted_pio_s1), .cpu_data_master_latency_counter (cpu_data_master_latency_counter), .cpu_data_master_qualified_request_pio_s1 (cpu_data_master_qualified_request_pio_s1), .cpu_data_master_read (cpu_data_master_read), .cpu_data_master_read_data_valid_pio_s1 (cpu_data_master_read_data_valid_pio_s1), .cpu_data_master_requests_pio_s1 (cpu_data_master_requests_pio_s1), .cpu_data_master_write (cpu_data_master_write), .cpu_data_master_writedata (cpu_data_master_writedata), .d1_pio_s1_end_xfer (d1_pio_s1_end_xfer), .pio_s1_address (pio_s1_address), .pio_s1_chipselect (pio_s1_chipselect), .pio_s1_readdata (pio_s1_readdata), .pio_s1_readdata_from_sa (pio_s1_readdata_from_sa), .pio_s1_reset_n (pio_s1_reset_n), .pio_s1_write_n (pio_s1_write_n), .pio_s1_writedata (pio_s1_writedata), .reset_n (clk_reset_n) ); pio the_pio ( .address (pio_s1_address), .chipselect (pio_s1_chipselect), .clk (clk), .in_port (in_port_to_the_pio), .out_port (out_port_from_the_pio), .readdata (pio_s1_readdata), .reset_n (pio_s1_reset_n), .write_n (pio_s1_write_n), .writedata (pio_s1_writedata) ); //reset is asserted asynchronously and deasserted synchronously cpu1_reset_clk_domain_synch_module cpu1_reset_clk_domain_synch ( .clk (clk), .data_in (1'b1), .data_out (clk_reset_n), .reset_n (reset_n_sources) ); //reset sources mux, which is an e_mux assign reset_n_sources = ~(~reset_n | 0 | cpu_jtag_debug_module_resetrequest_from_sa | cpu_jtag_debug_module_resetrequest_from_sa); endmodule //synthesis translate_off // <ALTERA_NOTE> CODE INSERTED BETWEEN HERE // AND HERE WILL BE PRESERVED </ALTERA_NOTE> // If user logic components use Altsync_Ram with convert_hex2ver.dll, // set USE_convert_hex2ver in the user comments section above // `ifdef USE_convert_hex2ver // `else // `define NO_PLI 1 // `endif `include "c:/altera/72sp1/quartus/eda/sim_lib/altera_mf.v" `include "c:/altera/72sp1/quartus/eda/sim_lib/220model.v" `include "c:/altera/72sp1/quartus/eda/sim_lib/sgate.v" `include "onchip_mem.v" `include "pio.v" `include "cpu_test_bench.v" `include "cpu_mult_cell.v" `include "cpu_jtag_debug_module.v" `include "cpu_jtag_debug_module_wrapper.v" `include "cpu.v" `include "jtag_uart.v" `timescale 1ns / 1ps module test_bench ; reg clk; wire [ 31: 0] in_port_to_the_pio; wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa; wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa; wire [ 31: 0] out_port_from_the_pio; reg reset_n; // <ALTERA_NOTE> CODE INSERTED BETWEEN HERE // add your signals and additional architecture here // AND HERE WILL BE PRESERVED </ALTERA_NOTE> //Set us up the Dut cpu1 DUT ( .clk (clk), .in_port_to_the_pio (in_port_to_the_pio), .out_port_from_the_pio (out_port_from_the_pio), .reset_n (reset_n) ); initial clk = 1'b0; always #10 clk <= ~clk; initial begin reset_n <= 0; #200 reset_n <= 1; end endmodule //synthesis translate_on
cpu_jtag_debug_module.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_jtag_debug_module ( // inputs: MonDReg, break_readreg, clk, clrn, dbrk_hit0_latch, dbrk_hit1_latch, dbrk_hit2_latch, dbrk_hit3_latch, debugack, ena, ir_in, jtag_state_sdr, jtag_state_udr, monitor_error, monitor_ready, raw_tck, reset_n, resetlatch, rti, shift, tdi, tracemem_on, tracemem_trcdata, tracemem_tw, trc_im_addr, trc_on, trc_wrap, trigbrktype, trigger_state_1, update, usr1, // outputs: ir_out, irq, jdo, jrst_n, st_ready_test_idle, take_action_break_a, take_action_break_b, take_action_break_c, take_action_ocimem_a, take_action_ocimem_b, take_action_tracectrl, take_action_tracemem_a, take_action_tracemem_b, take_no_action_break_a, take_no_action_break_b, take_no_action_break_c, take_no_action_ocimem_a, take_no_action_tracemem_a, tdo ) ; parameter SLD_AUTO_INSTANCE_INDEX = "YES"; parameter SLD_NODE_INFO = 286279168; output [ 1: 0] ir_out; output irq; output [ 37: 0] jdo; output jrst_n; output st_ready_test_idle; output take_action_break_a; output take_action_break_b; output take_action_break_c; output take_action_ocimem_a; output take_action_ocimem_b; output take_action_tracectrl; output take_action_tracemem_a; output take_action_tracemem_b; output take_no_action_break_a; output take_no_action_break_b; output take_no_action_break_c; output take_no_action_ocimem_a; output take_no_action_tracemem_a; output tdo; input [ 31: 0] MonDReg; input [ 31: 0] break_readreg; input clk; input clrn; input dbrk_hit0_latch; input dbrk_hit1_latch; input dbrk_hit2_latch; input dbrk_hit3_latch; input debugack; input ena; input [ 1: 0] ir_in; input jtag_state_sdr; input jtag_state_udr; input monitor_error; input monitor_ready; input raw_tck; input reset_n; input resetlatch; input rti; input shift; input tdi; input tracemem_on; input [ 35: 0] tracemem_trcdata; input tracemem_tw; input [ 6: 0] trc_im_addr; input trc_on; input trc_wrap; input trigbrktype; input trigger_state_1; input update; input usr1; reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; reg dr_update1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; reg dr_update2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; reg in_between_shiftdr_and_updatedr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */; reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; reg [ 1: 0] ir_out /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; wire irq; reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D103" */; wire jrst_n; reg jxdr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */; reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; wire st_ready_test_idle; reg st_shiftdr; reg st_updatedr; reg st_updateir; wire take_action_break_a; wire take_action_break_b; wire take_action_break_c; wire take_action_ocimem_a; wire take_action_ocimem_b; wire take_action_tracectrl; wire take_action_tracemem_a; wire take_action_tracemem_b; wire take_no_action_break_a; wire take_no_action_break_b; wire take_no_action_break_c; wire take_no_action_ocimem_a; wire take_no_action_tracemem_a; wire tdo; always @(posedge clk) begin dr_update1 <= st_updatedr; dr_update2 <= dr_update1; jxdr <= ~dr_update1 & dr_update2; end assign take_action_ocimem_a = jxdr && (ir == 2'b00) && ~jdo[35] && jdo[34]; assign take_no_action_ocimem_a = jxdr && (ir == 2'b00) && ~jdo[35] && ~jdo[34]; assign take_action_ocimem_b = jxdr && (ir == 2'b00) && jdo[35]; assign take_action_tracemem_a = jxdr && (ir == 2'b01) && ~jdo[37] && jdo[36]; assign take_no_action_tracemem_a = jxdr && (ir == 2'b01) && ~jdo[37] && ~jdo[36]; assign take_action_tracemem_b = jxdr && (ir == 2'b01) && jdo[37]; assign take_action_break_a = jxdr && (ir == 2'b10) && ~jdo[36] && jdo[37]; assign take_no_action_break_a = jxdr && (ir == 2'b10) && ~jdo[36] && ~jdo[37]; assign take_action_break_b = jxdr && (ir == 2'b10) && jdo[36] && ~jdo[35] && jdo[37]; assign take_no_action_break_b = jxdr && (ir == 2'b10) && jdo[36] && ~jdo[35] && ~jdo[37]; assign take_action_break_c = jxdr && (ir == 2'b10) && jdo[36] && jdo[35] && jdo[37]; assign take_no_action_break_c = jxdr && (ir == 2'b10) && jdo[36] && jdo[35] && ~jdo[37]; assign take_action_tracectrl = jxdr && (ir == 2'b11) && jdo[15]; always @(posedge raw_tck or negedge jrst_n) begin if (jrst_n == 0) ir_out <= 2'b0; else ir_out <= {debugack, monitor_ready}; end always @(posedge raw_tck or negedge jrst_n) begin if (jrst_n == 0) begin sr <= 0; DRsize <= 3'b000; end else if (st_updateir) begin case (ir_in) 2'b00: begin DRsize <= 3'b100; end // 2'b00 2'b01: begin DRsize <= 3'b101; end // 2'b01 2'b10: begin DRsize <= 3'b101; end // 2'b10 2'b11: begin DRsize <= 3'b010; end // 2'b11 endcase // ir_in ir <= ir_in; end else if (~shift & ~usr1 & ena & ~in_between_shiftdr_and_updatedr) case (ir) 2'b00: begin sr[35] <= debugack; sr[34] <= monitor_error; sr[33] <= resetlatch; sr[32 : 1] <= MonDReg; sr[0] <= monitor_ready; end // 2'b00 2'b01: begin sr[35 : 0] <= tracemem_trcdata; sr[37] <= tracemem_tw; sr[36] <= tracemem_on; end // 2'b01 2'b10: begin sr[37] <= trigger_state_1; sr[36] <= dbrk_hit3_latch; sr[35] <= dbrk_hit2_latch; sr[34] <= dbrk_hit1_latch; sr[33] <= dbrk_hit0_latch; sr[32 : 1] <= break_readreg; sr[0] <= trigbrktype; end // 2'b10 2'b11: begin sr[15 : 12] <= 1'b0; sr[11 : 2] <= trc_im_addr; sr[1] <= trc_wrap; sr[0] <= trc_on; end // 2'b11 endcase // ir else if (shift & ~usr1 & ena) case (DRsize) 3'b000: begin sr <= {tdi, sr[37 : 2], tdi}; end // 3'b000 3'b001: begin sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; end // 3'b001 3'b010: begin sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; end // 3'b010 3'b011: begin sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; end // 3'b011 3'b100: begin sr <= {tdi, sr[37], tdi, sr[35 : 1]}; end // 3'b100 3'b101: begin sr <= {tdi, sr[37 : 1]}; end // 3'b101 default: begin sr <= {tdi, sr[37 : 2], tdi}; end // default endcase // DRsize end assign tdo = sr[0]; assign st_ready_test_idle = rti; always @(posedge raw_tck) begin if (st_updatedr) jdo <= sr; end always @(posedge raw_tck) begin st_updatedr <= ~usr1 & ena & jtag_state_udr; st_updateir <= usr1 & ena & jtag_state_udr; st_shiftdr <= ~usr1 & ena & jtag_state_sdr; end always @(posedge raw_tck or negedge jrst_n) begin if (jrst_n == 0) in_between_shiftdr_and_updatedr <= 1'b0; else if (st_shiftdr) in_between_shiftdr_and_updatedr <= 1'b1; else if (st_updatedr) in_between_shiftdr_and_updatedr <= 1'b0; end //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS assign jrst_n = reset_n; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // assign jrst_n = clrn; //synthesis read_comments_as_HDL off endmodule
cpu_jtag_debug_module_wrapper.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_jtag_debug_module_wrapper ( // inputs: MonDReg, break_readreg, clk, dbrk_hit0_latch, dbrk_hit1_latch, dbrk_hit2_latch, dbrk_hit3_latch, debugack, monitor_error, monitor_ready, reset_n, resetlatch, tracemem_on, tracemem_trcdata, tracemem_tw, trc_im_addr, trc_on, trc_wrap, trigbrktype, trigger_state_1, // outputs: jdo, jrst_n, st_ready_test_idle, take_action_break_a, take_action_break_b, take_action_break_c, take_action_ocimem_a, take_action_ocimem_b, take_action_tracectrl, take_action_tracemem_a, take_action_tracemem_b, take_no_action_break_a, take_no_action_break_b, take_no_action_break_c, take_no_action_ocimem_a, take_no_action_tracemem_a ) ; output [ 37: 0] jdo; output jrst_n; output st_ready_test_idle; output take_action_break_a; output take_action_break_b; output take_action_break_c; output take_action_ocimem_a; output take_action_ocimem_b; output take_action_tracectrl; output take_action_tracemem_a; output take_action_tracemem_b; output take_no_action_break_a; output take_no_action_break_b; output take_no_action_break_c; output take_no_action_ocimem_a; output take_no_action_tracemem_a; input [ 31: 0] MonDReg; input [ 31: 0] break_readreg; input clk; input dbrk_hit0_latch; input dbrk_hit1_latch; input dbrk_hit2_latch; input dbrk_hit3_latch; input debugack; input monitor_error; input monitor_ready; input reset_n; input resetlatch; input tracemem_on; input [ 35: 0] tracemem_trcdata; input tracemem_tw; input [ 6: 0] trc_im_addr; input trc_on; input trc_wrap; input trigbrktype; input trigger_state_1; wire [ 37: 0] jdo; wire jrst_n; wire st_ready_test_idle; wire take_action_break_a; wire take_action_break_b; wire take_action_break_c; wire take_action_ocimem_a; wire take_action_ocimem_b; wire take_action_tracectrl; wire take_action_tracemem_a; wire take_action_tracemem_b; wire take_no_action_break_a; wire take_no_action_break_b; wire take_no_action_break_c; wire take_no_action_ocimem_a; wire take_no_action_tracemem_a; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS cpu_jtag_debug_module the_cpu_jtag_debug_module ( .MonDReg (MonDReg), .break_readreg (break_readreg), .clk (clk), .clrn (reset_n), .dbrk_hit0_latch (dbrk_hit0_latch), .dbrk_hit1_latch (dbrk_hit1_latch), .dbrk_hit2_latch (dbrk_hit2_latch), .dbrk_hit3_latch (dbrk_hit3_latch), .debugack (debugack), .ena (1'b0), .ir_in (2'b0), .jdo (jdo), .jrst_n (jrst_n), .jtag_state_sdr (1'b0), .jtag_state_udr (1'b0), .monitor_error (monitor_error), .monitor_ready (monitor_ready), .raw_tck (1'b0), .reset_n (reset_n), .resetlatch (resetlatch), .rti (1'b0), .shift (1'b0), .st_ready_test_idle (st_ready_test_idle), .take_action_break_a (take_action_break_a), .take_action_break_b (take_action_break_b), .take_action_break_c (take_action_break_c), .take_action_ocimem_a (take_action_ocimem_a), .take_action_ocimem_b (take_action_ocimem_b), .take_action_tracectrl (take_action_tracectrl), .take_action_tracemem_a (take_action_tracemem_a), .take_action_tracemem_b (take_action_tracemem_b), .take_no_action_break_a (take_no_action_break_a), .take_no_action_break_b (take_no_action_break_b), .take_no_action_break_c (take_no_action_break_c), .take_no_action_ocimem_a (take_no_action_ocimem_a), .take_no_action_tracemem_a (take_no_action_tracemem_a), .tdi (1'b0), .tracemem_on (tracemem_on), .tracemem_trcdata (tracemem_trcdata), .tracemem_tw (tracemem_tw), .trc_im_addr (trc_im_addr), .trc_on (trc_on), .trc_wrap (trc_wrap), .trigbrktype (trigbrktype), .trigger_state_1 (trigger_state_1), .update (1'b0), .usr1 (1'b0) ); //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // cpu_jtag_debug_module the_cpu_jtag_debug_module1 // ( // .MonDReg (MonDReg), // .break_readreg (break_readreg), // .clk (clk), // .dbrk_hit0_latch (dbrk_hit0_latch), // .dbrk_hit1_latch (dbrk_hit1_latch), // .dbrk_hit2_latch (dbrk_hit2_latch), // .dbrk_hit3_latch (dbrk_hit3_latch), // .debugack (debugack), // .jdo (jdo), // .jrst_n (jrst_n), // .monitor_error (monitor_error), // .monitor_ready (monitor_ready), // .reset_n (reset_n), // .resetlatch (resetlatch), // .st_ready_test_idle (st_ready_test_idle), // .take_action_break_a (take_action_break_a), // .take_action_break_b (take_action_break_b), // .take_action_break_c (take_action_break_c), // .take_action_ocimem_a (take_action_ocimem_a), // .take_action_ocimem_b (take_action_ocimem_b), // .take_action_tracectrl (take_action_tracectrl), // .take_action_tracemem_a (take_action_tracemem_a), // .take_action_tracemem_b (take_action_tracemem_b), // .take_no_action_break_a (take_no_action_break_a), // .take_no_action_break_b (take_no_action_break_b), // .take_no_action_break_c (take_no_action_break_c), // .take_no_action_ocimem_a (take_no_action_ocimem_a), // .take_no_action_tracemem_a (take_no_action_tracemem_a), // .tracemem_on (tracemem_on), // .tracemem_trcdata (tracemem_trcdata), // .tracemem_tw (tracemem_tw), // .trc_im_addr (trc_im_addr), // .trc_on (trc_on), // .trc_wrap (trc_wrap), // .trigbrktype (trigbrktype), // .trigger_state_1 (trigger_state_1) // ); // //synthesis read_comments_as_HDL off endmodule
cpu_mult_cell.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_mult_cell ( // inputs: A_mul_src1, A_mul_src2, clk, reset_n, // outputs: A_mul_cell_result ) ; output [ 31: 0] A_mul_cell_result; input [ 31: 0] A_mul_src1; input [ 31: 0] A_mul_src2; input clk; input reset_n; wire [ 31: 0] A_mul_cell_result; wire [ 31: 0] A_mul_cell_result_part_1; wire [ 15: 0] A_mul_cell_result_part_2; wire mul_clr; assign mul_clr = ~reset_n; altmult_add the_altmult_add_part_1 ( .aclr0 (mul_clr), .clock0 (clk), .dataa (A_mul_src1[15 : 0]), .datab (A_mul_src2[15 : 0]), .ena0 (1'b1), .result (A_mul_cell_result_part_1) ); defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0", the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0", the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED", the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES", the_altmult_add_part_1.input_register_a0 = "UNREGISTERED", the_altmult_add_part_1.input_register_b0 = "UNREGISTERED", the_altmult_add_part_1.input_source_a0 = "DATAA", the_altmult_add_part_1.input_source_b0 = "DATAB", the_altmult_add_part_1.intended_device_family = "CYCLONEII", the_altmult_add_part_1.lpm_type = "altmult_add", the_altmult_add_part_1.multiplier1_direction = "ADD", the_altmult_add_part_1.multiplier_aclr0 = "ACLR0", the_altmult_add_part_1.multiplier_register0 = "CLOCK0", the_altmult_add_part_1.number_of_multipliers = 1, the_altmult_add_part_1.output_register = "UNREGISTERED", the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED", the_altmult_add_part_1.port_signa = "PORT_UNUSED", the_altmult_add_part_1.port_signb = "PORT_UNUSED", the_altmult_add_part_1.representation_a = "UNSIGNED", the_altmult_add_part_1.representation_b = "UNSIGNED", the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0", the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0", the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0", the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0", the_altmult_add_part_1.signed_register_a = "UNREGISTERED", the_altmult_add_part_1.signed_register_b = "UNREGISTERED", the_altmult_add_part_1.width_a = 16, the_altmult_add_part_1.width_b = 16, the_altmult_add_part_1.width_result = 32; altmult_add the_altmult_add_part_2 ( .aclr0 (mul_clr), .clock0 (clk), .dataa (A_mul_src1[31 : 16]), .datab (A_mul_src2[15 : 0]), .ena0 (1'b1), .result (A_mul_cell_result_part_2) ); defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0", the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0", the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED", the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES", the_altmult_add_part_2.input_register_a0 = "UNREGISTERED", the_altmult_add_part_2.input_register_b0 = "UNREGISTERED", the_altmult_add_part_2.input_source_a0 = "DATAA", the_altmult_add_part_2.input_source_b0 = "DATAB", the_altmult_add_part_2.intended_device_family = "CYCLONEII", the_altmult_add_part_2.lpm_type = "altmult_add", the_altmult_add_part_2.multiplier1_direction = "ADD", the_altmult_add_part_2.multiplier_aclr0 = "ACLR0", the_altmult_add_part_2.multiplier_register0 = "CLOCK0", the_altmult_add_part_2.number_of_multipliers = 1, the_altmult_add_part_2.output_register = "UNREGISTERED", the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED", the_altmult_add_part_2.port_signa = "PORT_UNUSED", the_altmult_add_part_2.port_signb = "PORT_UNUSED", the_altmult_add_part_2.representation_a = "UNSIGNED", the_altmult_add_part_2.representation_b = "UNSIGNED", the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0", the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0", the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0", the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0", the_altmult_add_part_2.signed_register_a = "UNREGISTERED", the_altmult_add_part_2.signed_register_b = "UNREGISTERED", the_altmult_add_part_2.width_a = 16, the_altmult_add_part_2.width_b = 16, the_altmult_add_part_2.width_result = 16; assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] + A_mul_cell_result_part_2, A_mul_cell_result_part_1[15 : 0]}; endmodule
cpu_test_bench.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module cpu_test_bench ( // inputs: A_bstatus_reg, A_cmp_result, A_ctrl_exception, A_ctrl_ld_non_bypass, A_dst_regnum, A_en, A_estatus_reg, A_ienable_reg, A_ipending_reg, A_iw, A_mem_byte_en, A_op_hbreak, A_op_intr, A_pcb, A_st_data, A_status_reg, A_valid, A_wr_data_unfiltered, A_wr_dst_reg, E_add_br_to_taken_history_unfiltered, E_logic_result, E_valid, M_bht_ptr_unfiltered, M_bht_wr_data_unfiltered, M_bht_wr_en_unfiltered, M_mem_baddr, M_target_pcb, M_valid, W_dst_regnum, W_iw, W_iw_op, W_iw_opx, W_pcb, W_valid, W_wr_dst_reg, clk, d_address, d_byteenable, d_read, d_write, i_address, i_read, i_readdatavalid, reset_n, // outputs: A_wr_data_filtered, E_add_br_to_taken_history_filtered, E_src1_eq_src2, M_bht_ptr_filtered, M_bht_wr_data_filtered, M_bht_wr_en_filtered ) ; output [ 31: 0] A_wr_data_filtered; output E_add_br_to_taken_history_filtered; output E_src1_eq_src2; output [ 7: 0] M_bht_ptr_filtered; output [ 1: 0] M_bht_wr_data_filtered; output M_bht_wr_en_filtered; input A_bstatus_reg; input A_cmp_result; input A_ctrl_exception; input A_ctrl_ld_non_bypass; input [ 4: 0] A_dst_regnum; input A_en; input A_estatus_reg; input [ 31: 0] A_ienable_reg; input [ 31: 0] A_ipending_reg; input [ 31: 0] A_iw; input [ 3: 0] A_mem_byte_en; input A_op_hbreak; input A_op_intr; input [ 16: 0] A_pcb; input [ 31: 0] A_st_data; input A_status_reg; input A_valid; input [ 31: 0] A_wr_data_unfiltered; input A_wr_dst_reg; input E_add_br_to_taken_history_unfiltered; input [ 31: 0] E_logic_result; input E_valid; input [ 7: 0] M_bht_ptr_unfiltered; input [ 1: 0] M_bht_wr_data_unfiltered; input M_bht_wr_en_unfiltered; input [ 16: 0] M_mem_baddr; input [ 16: 0] M_target_pcb; input M_valid; input [ 4: 0] W_dst_regnum; input [ 31: 0] W_iw; input [ 5: 0] W_iw_op; input [ 5: 0] W_iw_opx; input [ 16: 0] W_pcb; input W_valid; input W_wr_dst_reg; input clk; input [ 16: 0] d_address; input [ 3: 0] d_byteenable; input d_read; input d_write; input [ 16: 0] i_address; input i_read; input i_readdatavalid; input reset_n; reg [ 16: 0] A_mem_baddr; reg [ 16: 0] A_target_pcb; wire [ 31: 0] A_wr_data_filtered; wire A_wr_data_unfiltered_0_is_x; wire A_wr_data_unfiltered_10_is_x; wire A_wr_data_unfiltered_11_is_x; wire A_wr_data_unfiltered_12_is_x; wire A_wr_data_unfiltered_13_is_x; wire A_wr_data_unfiltered_14_is_x; wire A_wr_data_unfiltered_15_is_x; wire A_wr_data_unfiltered_16_is_x; wire A_wr_data_unfiltered_17_is_x; wire A_wr_data_unfiltered_18_is_x; wire A_wr_data_unfiltered_19_is_x; wire A_wr_data_unfiltered_1_is_x; wire A_wr_data_unfiltered_20_is_x; wire A_wr_data_unfiltered_21_is_x; wire A_wr_data_unfiltered_22_is_x; wire A_wr_data_unfiltered_23_is_x; wire A_wr_data_unfiltered_24_is_x; wire A_wr_data_unfiltered_25_is_x; wire A_wr_data_unfiltered_26_is_x; wire A_wr_data_unfiltered_27_is_x; wire A_wr_data_unfiltered_28_is_x; wire A_wr_data_unfiltered_29_is_x; wire A_wr_data_unfiltered_2_is_x; wire A_wr_data_unfiltered_30_is_x; wire A_wr_data_unfiltered_31_is_x; wire A_wr_data_unfiltered_3_is_x; wire A_wr_data_unfiltered_4_is_x; wire A_wr_data_unfiltered_5_is_x; wire A_wr_data_unfiltered_6_is_x; wire A_wr_data_unfiltered_7_is_x; wire A_wr_data_unfiltered_8_is_x; wire A_wr_data_unfiltered_9_is_x; wire E_add_br_to_taken_history_filtered; wire E_src1_eq_src2; wire [ 7: 0] M_bht_ptr_filtered; wire [ 1: 0] M_bht_wr_data_filtered; wire M_bht_wr_en_filtered; wire [ 55: 0] W_inst; wire W_op_add; wire W_op_addi; wire W_op_and; wire W_op_andhi; wire W_op_andi; wire W_op_beq; wire W_op_bge; wire W_op_bgeu; wire W_op_blt; wire W_op_bltu; wire W_op_bne; wire W_op_br; wire W_op_break; wire W_op_bret; wire W_op_call; wire W_op_callr; wire W_op_cmpeq; wire W_op_cmpeqi; wire W_op_cmpge; wire W_op_cmpgei; wire W_op_cmpgeu; wire W_op_cmpgeui; wire W_op_cmplt; wire W_op_cmplti; wire W_op_cmpltu; wire W_op_cmpltui; wire W_op_cmpne; wire W_op_cmpnei; wire W_op_crst; wire W_op_custom; wire W_op_div; wire W_op_divu; wire W_op_eret; wire W_op_flushd; wire W_op_flushda; wire W_op_flushi; wire W_op_flushp; wire W_op_hbreak; wire W_op_initd; wire W_op_initi; wire W_op_intr; wire W_op_jmp; wire W_op_jmpi; wire W_op_ldb; wire W_op_ldbio; wire W_op_ldbu; wire W_op_ldbuio; wire W_op_ldh; wire W_op_ldhio; wire W_op_ldhu; wire W_op_ldhuio; wire W_op_ldw; wire W_op_ldwio; wire W_op_mul; wire W_op_muli; wire W_op_mulxss; wire W_op_mulxsu; wire W_op_mulxuu; wire W_op_nextpc; wire W_op_nor; wire W_op_opx; wire W_op_or; wire W_op_orhi; wire W_op_ori; wire W_op_rdctl; wire W_op_ret; wire W_op_rol; wire W_op_roli; wire W_op_ror; wire W_op_rsv02; wire W_op_rsv09; wire W_op_rsv10; wire W_op_rsv17; wire W_op_rsv18; wire W_op_rsv19; wire W_op_rsv25; wire W_op_rsv26; wire W_op_rsv29; wire W_op_rsv31; wire W_op_rsv33; wire W_op_rsv34; wire W_op_rsv41; wire W_op_rsv42; wire W_op_rsv49; wire W_op_rsv56; wire W_op_rsv57; wire W_op_rsv61; wire W_op_rsv62; wire W_op_rsv63; wire W_op_rsvx00; wire W_op_rsvx10; wire W_op_rsvx15; wire W_op_rsvx17; wire W_op_rsvx20; wire W_op_rsvx21; wire W_op_rsvx25; wire W_op_rsvx33; wire W_op_rsvx34; wire W_op_rsvx35; wire W_op_rsvx42; wire W_op_rsvx43; wire W_op_rsvx44; wire W_op_rsvx47; wire W_op_rsvx50; wire W_op_rsvx51; wire W_op_rsvx55; wire W_op_rsvx56; wire W_op_rsvx60; wire W_op_rsvx63; wire W_op_sll; wire W_op_slli; wire W_op_sra; wire W_op_srai; wire W_op_srl; wire W_op_srli; wire W_op_stb; wire W_op_stbio; wire W_op_sth; wire W_op_sthio; wire W_op_stw; wire W_op_stwio; wire W_op_sub; wire W_op_sync; wire W_op_trap; wire W_op_wrctl; wire W_op_xor; wire W_op_xorhi; wire W_op_xori; wire [ 55: 0] W_vinst; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) A_target_pcb <= 0; else if (A_en) A_target_pcb <= M_target_pcb; end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) A_mem_baddr <= 0; else if (A_en) A_mem_baddr <= M_mem_baddr; end assign E_src1_eq_src2 = E_logic_result == 0; //Propagating 'X' data bits assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered; //Propagating 'X' data bits assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered; //Propagating 'X' data bits assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered; //Propagating 'X' data bits assign M_bht_ptr_filtered = M_bht_ptr_unfiltered; assign W_op_rsv02 = W_iw_op[5 : 0] == 2; assign W_op_cmplti = W_iw_op[5 : 0] == 16; assign W_op_rsv18 = W_iw_op[5 : 0] == 18; assign W_op_rsv26 = W_iw_op[5 : 0] == 26; assign W_op_rsv42 = W_iw_op[5 : 0] == 42; assign W_op_ldbio = W_iw_op[5 : 0] == 39; assign W_op_ldbu = W_iw_op[5 : 0] == 3; assign W_op_orhi = W_iw_op[5 : 0] == 52; assign W_op_rsv31 = W_iw_op[5 : 0] == 31; assign W_op_bge = W_iw_op[5 : 0] == 14; assign W_op_br = W_iw_op[5 : 0] == 6; assign W_op_ldhio = W_iw_op[5 : 0] == 47; assign W_op_rsv41 = W_iw_op[5 : 0] == 41; assign W_op_rsv19 = W_iw_op[5 : 0] == 19; assign W_op_ldwio = W_iw_op[5 : 0] == 55; assign W_op_rsv29 = W_iw_op[5 : 0] == 29; assign W_op_rsv61 = W_iw_op[5 : 0] == 61; assign W_op_opx = W_iw_op[5 : 0] == 58; assign W_op_stb = W_iw_op[5 : 0] == 5; assign W_op_rsv62 = W_iw_op[5 : 0] == 62; assign W_op_bltu = W_iw_op[5 : 0] == 54; assign W_op_custom = W_iw_op[5 : 0] == 50; assign W_op_muli = W_iw_op[5 : 0] == 36; assign W_op_xori = W_iw_op[5 : 0] == 28; assign W_op_cmpgei = W_iw_op[5 : 0] == 8; assign W_op_ldw = W_iw_op[5 : 0] == 23; assign W_op_cmpeqi = W_iw_op[5 : 0] == 32; assign W_op_ldh = W_iw_op[5 : 0] == 15; assign W_op_stw = W_iw_op[5 : 0] == 21; assign W_op_rsv09 = W_iw_op[5 : 0] == 9; assign W_op_cmpnei = W_iw_op[5 : 0] == 24; assign W_op_ldb = W_iw_op[5 : 0] == 7; assign W_op_bgeu = W_iw_op[5 : 0] == 46; assign W_op_stwio = W_iw_op[5 : 0] == 53; assign W_op_rsv33 = W_iw_op[5 : 0] == 33; assign W_op_andhi = W_iw_op[5 : 0] == 44; assign W_op_ldbuio = W_iw_op[5 : 0] == 35; assign W_op_rsv34 = W_iw_op[5 : 0] == 34; assign W_op_sthio = W_iw_op[5 : 0] == 45; assign W_op_cmpgeui = W_iw_op[5 : 0] == 40; assign W_op_stbio = W_iw_op[5 : 0] == 37; assign W_op_andi = W_iw_op[5 : 0] == 12; assign W_op_addi = W_iw_op[5 : 0] == 4; assign W_op_flushda = W_iw_op[5 : 0] == 27; assign W_op_rsv49 = W_iw_op[5 : 0] == 49; assign W_op_jmpi = W_iw_op[5 : 0] == 1; assign W_op_blt = W_iw_op[5 : 0] == 22; assign W_op_beq = W_iw_op[5 : 0] == 38; assign W_op_ori = W_iw_op[5 : 0] == 20; assign W_op_cmpltui = W_iw_op[5 : 0] == 48; assign W_op_xorhi = W_iw_op[5 : 0] == 60; assign W_op_rsv56 = W_iw_op[5 : 0] == 56; assign W_op_ldhuio = W_iw_op[5 : 0] == 43; assign W_op_rsv63 = W_iw_op[5 : 0] == 63; assign W_op_bne = W_iw_op[5 : 0] == 30; assign W_op_rsv57 = W_iw_op[5 : 0] == 57; assign W_op_call = W_iw_op[5 : 0] == 0; assign W_op_ldhu = W_iw_op[5 : 0] == 11; assign W_op_flushd = W_iw_op[5 : 0] == 59; assign W_op_initd = W_iw_op[5 : 0] == 51; assign W_op_rsv10 = W_iw_op[5 : 0] == 10; assign W_op_rsv17 = W_iw_op[5 : 0] == 17; assign W_op_sth = W_iw_op[5 : 0] == 13; assign W_op_rsv25 = W_iw_op[5 : 0] == 25; assign W_op_flushi = W_op_opx & (W_iw_opx[5 : 0] == 12); assign W_op_mulxuu = W_op_opx & (W_iw_opx[5 : 0] == 7); assign W_op_rsvx33 = W_op_opx & (W_iw_opx[5 : 0] == 33); assign W_op_wrctl = W_op_opx & (W_iw_opx[5 : 0] == 46); assign W_op_roli = W_op_opx & (W_iw_opx[5 : 0] == 2); assign W_op_intr = W_op_opx & (W_iw_opx[5 : 0] == 61); assign W_op_rsvx43 = W_op_opx & (W_iw_opx[5 : 0] == 43); assign W_op_srl = W_op_opx & (W_iw_opx[5 : 0] == 27); assign W_op_trap = W_op_opx & (W_iw_opx[5 : 0] == 45); assign W_op_rsvx17 = W_op_opx & (W_iw_opx[5 : 0] == 17); assign W_op_break = W_op_opx & (W_iw_opx[5 : 0] == 52); assign W_op_rdctl = W_op_opx & (W_iw_opx[5 : 0] == 38); assign W_op_cmpltu = W_op_opx & (W_iw_opx[5 : 0] == 48); assign W_op_callr = W_op_opx & (W_iw_opx[5 : 0] == 29); assign W_op_cmpge = W_op_opx & (W_iw_opx[5 : 0] == 8); assign W_op_rsvx47 = W_op_opx & (W_iw_opx[5 : 0] == 47); assign W_op_and = W_op_opx & (W_iw_opx[5 : 0] == 14); assign W_op_rsvx00 = W_op_opx & (W_iw_opx[5 : 0] == 0); assign W_op_rsvx56 = W_op_opx & (W_iw_opx[5 : 0] == 56); assign W_op_hbreak = W_op_opx & (W_iw_opx[5 : 0] == 53); assign W_op_flushp = W_op_opx & (W_iw_opx[5 : 0] == 4); assign W_op_nor = W_op_opx & (W_iw_opx[5 : 0] == 6); assign W_op_rsvx50 = W_op_opx & (W_iw_opx[5 : 0] == 50); assign W_op_initi = W_op_opx & (W_iw_opx[5 : 0] == 41); assign W_op_srai = W_op_opx & (W_iw_opx[5 : 0] == 58); assign W_op_sync = W_op_opx & (W_iw_opx[5 : 0] == 54); assign W_op_rsvx15 = W_op_opx & (W_iw_opx[5 : 0] == 15); assign W_op_rsvx55 = W_op_opx & (W_iw_opx[5 : 0] == 55); assign W_op_crst = W_op_opx & (W_iw_opx[5 : 0] == 62); assign W_op_rsvx42 = W_op_opx & (W_iw_opx[5 : 0] == 42); assign W_op_xor = W_op_opx & (W_iw_opx[5 : 0] == 30); assign W_op_rsvx34 = W_op_opx & (W_iw_opx[5 : 0] == 34); assign W_op_mulxss = W_op_opx & (W_iw_opx[5 : 0] == 31); assign W_op_rsvx51 = W_op_opx & (W_iw_opx[5 : 0] == 51); assign W_op_rsvx10 = W_op_opx & (W_iw_opx[5 : 0] == 10); assign W_op_eret = W_op_opx & (W_iw_opx[5 : 0] == 1); assign W_op_rsvx25 = W_op_opx & (W_iw_opx[5 : 0] == 25); assign W_op_jmp = W_op_opx & (W_iw_opx[5 : 0] == 13); assign W_op_or = W_op_opx & (W_iw_opx[5 : 0] == 22); assign W_op_rsvx35 = W_op_opx & (W_iw_opx[5 : 0] == 35); assign W_op_sra = W_op_opx & (W_iw_opx[5 : 0] == 59); assign W_op_rsvx20 = W_op_opx & (W_iw_opx[5 : 0] == 20); assign W_op_slli = W_op_opx & (W_iw_opx[5 : 0] == 18); assign W_op_mulxsu = W_op_opx & (W_iw_opx[5 : 0] == 23); assign W_op_rsvx21 = W_op_opx & (W_iw_opx[5 : 0] == 21); assign W_op_ror = W_op_opx & (W_iw_opx[5 : 0] == 11); assign W_op_srli = W_op_opx & (W_iw_opx[5 : 0] == 26); assign W_op_sll = W_op_opx & (W_iw_opx[5 : 0] == 19); assign W_op_div = W_op_opx & (W_iw_opx[5 : 0] == 37); assign W_op_cmplt = W_op_opx & (W_iw_opx[5 : 0] == 16); assign W_op_add = W_op_opx & (W_iw_opx[5 : 0] == 49); assign W_op_rsvx44 = W_op_opx & (W_iw_opx[5 : 0] == 44); assign W_op_bret = W_op_opx & (W_iw_opx[5 : 0] == 9); assign W_op_rsvx60 = W_op_opx & (W_iw_opx[5 : 0] == 60); assign W_op_rsvx63 = W_op_opx & (W_iw_opx[5 : 0] == 63); assign W_op_mul = W_op_opx & (W_iw_opx[5 : 0] == 39); assign W_op_cmpgeu = W_op_opx & (W_iw_opx[5 : 0] == 40); assign W_op_cmpne = W_op_opx & (W_iw_opx[5 : 0] == 24); assign W_op_cmpeq = W_op_opx & (W_iw_opx[5 : 0] == 32); assign W_op_ret = W_op_opx & (W_iw_opx[5 : 0] == 5); assign W_op_rol = W_op_opx & (W_iw_opx[5 : 0] == 3); assign W_op_sub = W_op_opx & (W_iw_opx[5 : 0] == 57); assign W_op_nextpc = W_op_opx & (W_iw_opx[5 : 0] == 28); assign W_op_divu = W_op_opx & (W_iw_opx[5 : 0] == 36); //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //Clearing 'X' data bits assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx; assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0]; assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx; assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1]; assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx; assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2]; assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx; assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3]; assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx; assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4]; assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx; assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5]; assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx; assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6]; assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx; assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7]; assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx; assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8]; assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx; assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9]; assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx; assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10]; assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx; assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11]; assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx; assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12]; assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx; assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13]; assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx; assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14]; assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx; assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15]; assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx; assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16]; assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx; assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17]; assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx; assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18]; assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx; assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19]; assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx; assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20]; assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx; assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21]; assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx; assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22]; assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx; assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23]; assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx; assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24]; assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx; assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25]; assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx; assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26]; assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx; assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27]; assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx; assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28]; assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx; assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29]; assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx; assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30]; assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx; assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31]; always @(posedge clk) begin if (reset_n) if (^(W_wr_dst_reg) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/W_wr_dst_reg is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_wr_dst_reg) if (^(W_dst_regnum) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/W_dst_regnum is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(W_valid) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/W_valid is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid) if (^(W_pcb) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/W_pcb is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (W_valid) if (^(W_iw) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/W_iw is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(A_en) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/A_en is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(E_valid) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/E_valid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(M_valid) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/M_valid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(A_valid) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/A_valid is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (A_valid & A_en & A_wr_dst_reg) if (^(A_wr_data_unfiltered) === 1'bx) begin $write("%0d ns: WARNING: cpu_test_bench/A_wr_data_unfiltered is 'x'\n", $time); end end always @(posedge clk) begin if (reset_n) if (^(A_status_reg) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/A_status_reg is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(A_estatus_reg) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/A_estatus_reg is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(A_bstatus_reg) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/A_bstatus_reg is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(i_read) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/i_read is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (i_read) if (^(i_address) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/i_address is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(i_readdatavalid) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/i_readdatavalid is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(d_write) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/d_write is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (d_write) if (^(d_byteenable) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/d_byteenable is 'x'\n", $time); $stop; end end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin end else if (d_write | d_read) if (^(d_address) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/d_address is 'x'\n", $time); $stop; end end always @(posedge clk) begin if (reset_n) if (^(d_read) === 1'bx) begin $write("%0d ns: ERROR: cpu_test_bench/d_read is 'x'\n", $time); $stop; end end reg [31:0] trace_handle; // for $fopen initial begin trace_handle = $fopen("cpu.tr"); $fwrite(trace_handle, "version 2\nnumThreads 1\n"); end always @(posedge clk) begin if (~reset_n || (A_valid & A_en)) $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, A_pcb, 0, A_op_intr, A_op_hbreak, A_iw, A_wr_dst_reg, A_dst_regnum, A_wr_data_filtered, A_mem_baddr, A_st_data, A_mem_byte_en, A_cmp_result, A_target_pcb, A_status_reg, A_estatus_reg, A_bstatus_reg, A_ienable_reg, A_ipending_reg, 0, 0, 0, 0, 0, 0, A_ctrl_exception); end assign W_inst = ((((W_iw_op[5 : 0] == 2))))? 56'h20207273763032 : ((((W_iw_op[5 : 0] == 16))))? 56'h20636d706c7469 : ((((W_iw_op[5 : 0] == 18))))? 56'h20207273763138 : ((((W_iw_op[5 : 0] == 26))))? 56'h20207273763236 : ((((W_iw_op[5 : 0] == 42))))? 56'h20207273763432 : ((((W_iw_op[5 : 0] == 39))))? 56'h20206c6462696f : ((((W_iw_op[5 : 0] == 3))))? 56'h2020206c646275 : ((((W_iw_op[5 : 0] == 52))))? 56'h2020206f726869 : ((((W_iw_op[5 : 0] == 31))))? 56'h20207273763331 : ((((W_iw_op[5 : 0] == 14))))? 56'h20202020626765 : ((((W_iw_op[5 : 0] == 6))))? 56'h20202020206272 : ((((W_iw_op[5 : 0] == 47))))? 56'h20206c6468696f : ((((W_iw_op[5 : 0] == 41))))? 56'h20207273763431 : ((((W_iw_op[5 : 0] == 19))))? 56'h20207273763139 : ((((W_iw_op[5 : 0] == 55))))? 56'h20206c6477696f : ((((W_iw_op[5 : 0] == 29))))? 56'h20207273763239 : ((((W_iw_op[5 : 0] == 61))))? 56'h20207273763631 : ((((W_iw_op[5 : 0] == 5))))? 56'h20202020737462 : ((((W_iw_op[5 : 0] == 62))))? 56'h20207273763632 : ((((W_iw_op[5 : 0] == 54))))? 56'h202020626c7475 : ((((W_iw_op[5 : 0] == 50))))? 56'h20637573746f6d : ((((W_iw_op[5 : 0] == 36))))? 56'h2020206d756c69 : ((((W_iw_op[5 : 0] == 28))))? 56'h202020786f7269 : ((((W_iw_op[5 : 0] == 8))))? 56'h20636d70676569 : ((((W_iw_op[5 : 0] == 23))))? 56'h202020206c6477 : ((((W_iw_op[5 : 0] == 32))))? 56'h20636d70657169 : ((((W_iw_op[5 : 0] == 15))))? 56'h202020206c6468 : ((((W_iw_op[5 : 0] == 21))))? 56'h20202020737477 : ((((W_iw_op[5 : 0] == 9))))? 56'h20207273763039 : ((((W_iw_op[5 : 0] == 24))))? 56'h20636d706e6569 : ((((W_iw_op[5 : 0] == 7))))? 56'h202020206c6462 : ((((W_iw_op[5 : 0] == 46))))? 56'h20202062676575 : ((((W_iw_op[5 : 0] == 53))))? 56'h2020737477696f : ((((W_iw_op[5 : 0] == 33))))? 56'h20207273763333 : ((((W_iw_op[5 : 0] == 44))))? 56'h2020616e646869 : ((((W_iw_op[5 : 0] == 35))))? 56'h206c646275696f : ((((W_iw_op[5 : 0] == 34))))? 56'h20207273763334 : ((((W_iw_op[5 : 0] == 45))))? 56'h2020737468696f : ((((W_iw_op[5 : 0] == 40))))? 56'h636d7067657569 : ((((W_iw_op[5 : 0] == 37))))? 56'h2020737462696f : ((((W_iw_op[5 : 0] == 12))))? 56'h202020616e6469 : ((((W_iw_op[5 : 0] == 4))))? 56'h20202061646469 : ((((W_iw_op[5 : 0] == 27))))? 56'h666c7573686461 : ((((W_iw_op[5 : 0] == 49))))? 56'h20207273763439 : ((((W_iw_op[5 : 0] == 1))))? 56'h2020206a6d7069 : ((((W_iw_op[5 : 0] == 22))))? 56'h20202020626c74 : ((((W_iw_op[5 : 0] == 38))))? 56'h20202020626571 : ((((W_iw_op[5 : 0] == 20))))? 56'h202020206f7269 : ((((W_iw_op[5 : 0] == 48))))? 56'h636d706c747569 : ((((W_iw_op[5 : 0] == 60))))? 56'h2020786f726869 : ((((W_iw_op[5 : 0] == 56))))? 56'h20207273763536 : ((((W_iw_op[5 : 0] == 43))))? 56'h206c646875696f : ((((W_iw_op[5 : 0] == 63))))? 56'h20207273763633 : ((((W_iw_op[5 : 0] == 30))))? 56'h20202020626e65 : ((((W_iw_op[5 : 0] == 57))))? 56'h20207273763537 : ((((W_iw_op[5 : 0] == 0))))? 56'h20202063616c6c : ((((W_iw_op[5 : 0] == 11))))? 56'h2020206c646875 : ((((W_iw_op[5 : 0] == 59))))? 56'h20666c75736864 : ((((W_iw_op[5 : 0] == 51))))? 56'h2020696e697464 : ((((W_iw_op[5 : 0] == 10))))? 56'h20207273763130 : ((((W_iw_op[5 : 0] == 17))))? 56'h20207273763137 : ((((W_iw_op[5 : 0] == 13))))? 56'h20202020737468 : ((((W_iw_op[5 : 0] == 25))))? 56'h20207273763235 : (((W_op_opx & (W_iw_opx[5 : 0] == 12))))? 56'h20666c75736869 : (((W_op_opx & (W_iw_opx[5 : 0] == 7))))? 56'h206d756c787575 : (((W_op_opx & (W_iw_opx[5 : 0] == 33))))? 56'h20727376783333 : (((W_op_opx & (W_iw_opx[5 : 0] == 46))))? 56'h2020777263746c : (((W_op_opx & (W_iw_opx[5 : 0] == 2))))? 56'h202020726f6c69 : (((W_op_opx & (W_iw_opx[5 : 0] == 61))))? 56'h202020696e7472 : (((W_op_opx & (W_iw_opx[5 : 0] == 43))))? 56'h20727376783433 : (((W_op_opx & (W_iw_opx[5 : 0] == 27))))? 56'h2020202073726c : (((W_op_opx & (W_iw_opx[5 : 0] == 45))))? 56'h20202074726170 : (((W_op_opx & (W_iw_opx[5 : 0] == 17))))? 56'h20727376783137 : (((W_op_opx & (W_iw_opx[5 : 0] == 52))))? 56'h2020627265616b : (((W_op_opx & (W_iw_opx[5 : 0] == 38))))? 56'h2020726463746c : (((W_op_opx & (W_iw_opx[5 : 0] == 48))))? 56'h20636d706c7475 : (((W_op_opx & (W_iw_opx[5 : 0] == 29))))? 56'h202063616c6c72 : (((W_op_opx & (W_iw_opx[5 : 0] == 8))))? 56'h2020636d706765 : (((W_op_opx & (W_iw_opx[5 : 0] == 47))))? 56'h20727376783437 : (((W_op_opx & (W_iw_opx[5 : 0] == 14))))? 56'h20202020616e64 : (((W_op_opx & (W_iw_opx[5 : 0] == 0))))? 56'h20727376783030 : (((W_op_opx & (W_iw_opx[5 : 0] == 56))))? 56'h20727376783536 : (((W_op_opx & (W_iw_opx[5 : 0] == 53))))? 56'h2068627265616b : (((W_op_opx & (W_iw_opx[5 : 0] == 4))))? 56'h20666c75736870 : (((W_op_opx & (W_iw_opx[5 : 0] == 6))))? 56'h202020206e6f72 : (((W_op_opx & (W_iw_opx[5 : 0] == 50))))? 56'h20727376783530 : (((W_op_opx & (W_iw_opx[5 : 0] == 41))))? 56'h2020696e697469 : (((W_op_opx & (W_iw_opx[5 : 0] == 58))))? 56'h20202073726169 : (((W_op_opx & (W_iw_opx[5 : 0] == 54))))? 56'h20202073796e63 : (((W_op_opx & (W_iw_opx[5 : 0] == 15))))? 56'h20727376783135 : (((W_op_opx & (W_iw_opx[5 : 0] == 55))))? 56'h20727376783535 : (((W_op_opx & (W_iw_opx[5 : 0] == 62))))? 56'h20202063727374 : (((W_op_opx & (W_iw_opx[5 : 0] == 42))))? 56'h20727376783432 : (((W_op_opx & (W_iw_opx[5 : 0] == 30))))? 56'h20202020786f72 : (((W_op_opx & (W_iw_opx[5 : 0] == 34))))? 56'h20727376783334 : (((W_op_opx & (W_iw_opx[5 : 0] == 31))))? 56'h206d756c787373 : (((W_op_opx & (W_iw_opx[5 : 0] == 51))))? 56'h20727376783531 : (((W_op_opx & (W_iw_opx[5 : 0] == 10))))? 56'h20727376783130 : (((W_op_opx & (W_iw_opx[5 : 0] == 1))))? 56'h20202065726574 : (((W_op_opx & (W_iw_opx[5 : 0] == 25))))? 56'h20727376783235 : (((W_op_opx & (W_iw_opx[5 : 0] == 13))))? 56'h202020206a6d70 : (((W_op_opx & (W_iw_opx[5 : 0] == 22))))? 56'h20202020206f72 : (((W_op_opx & (W_iw_opx[5 : 0] == 35))))? 56'h20727376783335 : (((W_op_opx & (W_iw_opx[5 : 0] == 59))))? 56'h20202020737261 : (((W_op_opx & (W_iw_opx[5 : 0] == 20))))? 56'h20727376783230 : (((W_op_opx & (W_iw_opx[5 : 0] == 18))))? 56'h202020736c6c69 : (((W_op_opx & (W_iw_opx[5 : 0] == 23))))? 56'h206d756c787375 : (((W_op_opx & (W_iw_opx[5 : 0] == 21))))? 56'h20727376783231 : (((W_op_opx & (W_iw_opx[5 : 0] == 11))))? 56'h20202020726f72 : (((W_op_opx & (W_iw_opx[5 : 0] == 26))))? 56'h20202073726c69 : (((W_op_opx & (W_iw_opx[5 : 0] == 19))))? 56'h20202020736c6c : (((W_op_opx & (W_iw_opx[5 : 0] == 37))))? 56'h20202020646976 : (((W_op_opx & (W_iw_opx[5 : 0] == 16))))? 56'h2020636d706c74 : (((W_op_opx & (W_iw_opx[5 : 0] == 49))))? 56'h20202020616464 : (((W_op_opx & (W_iw_opx[5 : 0] == 44))))? 56'h20727376783434 : (((W_op_opx & (W_iw_opx[5 : 0] == 9))))? 56'h20202062726574 : (((W_op_opx & (W_iw_opx[5 : 0] == 60))))? 56'h20727376783630 : (((W_op_opx & (W_iw_opx[5 : 0] == 63))))? 56'h20727376783633 : (((W_op_opx & (W_iw_opx[5 : 0] == 39))))? 56'h202020206d756c : (((W_op_opx & (W_iw_opx[5 : 0] == 40))))? 56'h20636d70676575 : (((W_op_opx & (W_iw_opx[5 : 0] == 24))))? 56'h2020636d706e65 : (((W_op_opx & (W_iw_opx[5 : 0] == 32))))? 56'h2020636d706571 : (((W_op_opx & (W_iw_opx[5 : 0] == 5))))? 56'h20202020726574 : (((W_op_opx & (W_iw_opx[5 : 0] == 3))))? 56'h20202020726f6c : (((W_op_opx & (W_iw_opx[5 : 0] == 57))))? 56'h20202020737562 : (((W_op_opx & (W_iw_opx[5 : 0] == 28))))? 56'h206e6578747063 : (((W_op_opx & (W_iw_opx[5 : 0] == 36))))? 56'h20202064697675 : 56'h20202020424144; assign W_vinst = W_valid ? W_inst : {7{8'h2d}}; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // // assign A_wr_data_filtered = A_wr_data_unfiltered; // //synthesis read_comments_as_HDL off endmodule
jtag_uart.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module jtag_uart_log_module ( // inputs: clk, data, strobe, valid ) ; input clk; input [ 7: 0] data; input strobe; input valid; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS reg [31:0] text_handle; // for $fopen initial text_handle = $fopen ("C:/ece314/nios2lab1/cpu1_sim/jtag_uart_output_stream.dat"); always @(posedge clk) begin if (valid && strobe) begin $fwrite (text_handle, "%b\n", data); // echo raw binary strings to file as ascii to screen $write("%s", ((data == 8'hd) ? 8'ha : data)); // non-standard; poorly documented; required to get real data stream. $fflush (text_handle); end end // clk //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module jtag_uart_sim_scfifo_w ( // inputs: clk, fifo_wdata, fifo_wr, // outputs: fifo_FF, r_dat, wfifo_empty, wfifo_used ) ; output fifo_FF; output [ 7: 0] r_dat; output wfifo_empty; output [ 5: 0] wfifo_used; input clk; input [ 7: 0] fifo_wdata; input fifo_wr; wire fifo_FF; wire [ 7: 0] r_dat; wire wfifo_empty; wire [ 5: 0] wfifo_used; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //jtag_uart_log, which is an e_log jtag_uart_log_module jtag_uart_log ( .clk (clk), .data (fifo_wdata), .strobe (fifo_wr), .valid (fifo_wr) ); assign wfifo_used = {6{1'b0}}; assign r_dat = {8{1'b0}}; assign fifo_FF = 1'b0; assign wfifo_empty = 1'b1; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module jtag_uart_scfifo_w ( // inputs: clk, fifo_clear, fifo_wdata, fifo_wr, rd_wfifo, // outputs: fifo_FF, r_dat, wfifo_empty, wfifo_used ) ; output fifo_FF; output [ 7: 0] r_dat; output wfifo_empty; output [ 5: 0] wfifo_used; input clk; input fifo_clear; input [ 7: 0] fifo_wdata; input fifo_wr; input rd_wfifo; wire fifo_FF; wire [ 7: 0] r_dat; wire wfifo_empty; wire [ 5: 0] wfifo_used; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS jtag_uart_sim_scfifo_w the_jtag_uart_sim_scfifo_w ( .clk (clk), .fifo_FF (fifo_FF), .fifo_wdata (fifo_wdata), .fifo_wr (fifo_wr), .r_dat (r_dat), .wfifo_empty (wfifo_empty), .wfifo_used (wfifo_used) ); //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // scfifo wfifo // ( // .aclr (fifo_clear), // .clock (clk), // .data (fifo_wdata), // .empty (wfifo_empty), // .full (fifo_FF), // .q (r_dat), // .rdreq (rd_wfifo), // .usedw (wfifo_used), // .wrreq (fifo_wr) // ); // // defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", // wfifo.lpm_numwords = 64, // wfifo.lpm_showahead = "OFF", // wfifo.lpm_type = "scfifo", // wfifo.lpm_width = 8, // wfifo.lpm_widthu = 6, // wfifo.overflow_checking = "OFF", // wfifo.underflow_checking = "OFF", // wfifo.use_eab = "ON"; // //synthesis read_comments_as_HDL off endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module jtag_uart_drom_module ( // inputs: clk, incr_addr, reset_n, // outputs: new_rom, num_bytes, q, safe ) ; parameter POLL_RATE = 100; output new_rom; output [ 31: 0] num_bytes; output [ 7: 0] q; output safe; input clk; input incr_addr; input reset_n; reg [ 11: 0] address; reg d1_pre; reg d2_pre; reg d3_pre; reg d4_pre; reg d5_pre; reg d6_pre; reg d7_pre; reg d8_pre; reg d9_pre; reg [ 7: 0] mem_array [2047: 0]; reg [ 31: 0] mutex [ 1: 0]; reg new_rom; wire [ 31: 0] num_bytes; reg pre; wire [ 7: 0] q; wire safe; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS assign q = mem_array[address]; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) begin d1_pre <= 0; d2_pre <= 0; d3_pre <= 0; d4_pre <= 0; d5_pre <= 0; d6_pre <= 0; d7_pre <= 0; d8_pre <= 0; d9_pre <= 0; new_rom <= 0; end else if (1) begin d1_pre <= pre; d2_pre <= d1_pre; d3_pre <= d2_pre; d4_pre <= d3_pre; d5_pre <= d4_pre; d6_pre <= d5_pre; d7_pre <= d6_pre; d8_pre <= d7_pre; d9_pre <= d8_pre; new_rom <= d9_pre; end end assign num_bytes = mutex[1]; reg safe_delay; reg [31:0] poll_count; reg [31:0] mutex_handle; wire interactive = 1'b0 ; // ' assign safe = (address < mutex[1]); initial poll_count = POLL_RATE; always @(posedge clk or negedge reset_n) begin if (reset_n !== 1) begin safe_delay <= 0; end else begin safe_delay <= safe; end end // safe_delay always @(posedge clk or negedge reset_n) begin if (reset_n !== 1) begin // dont worry about null _stream.dat file address <= 0; mem_array[0] <= 0; mutex[0] <= 0; mutex[1] <= 0; pre <= 0; end else begin // deal with the non-reset case pre <= 0; if (incr_addr && safe) address <= address + 1; if (mutex[0] && !safe && safe_delay) begin // and blast the mutex after falling edge of safe if interactive if (interactive) begin mutex_handle = $fopen ("C:/ece314/nios2lab1/cpu1_sim/jtag_uart_input_mutex.dat"); $fdisplay (mutex_handle, "0"); $fclose (mutex_handle); // $display ($stime, "\t%m:\n\t\tMutex cleared!"); end else begin // sleep until next reset, do not bash mutex. wait (!reset_n); end end // OK to bash mutex. if (poll_count < POLL_RATE) begin // wait poll_count = poll_count + 1; end else begin // do the interesting stuff. poll_count = 0; $readmemh ("C:/ece314/nios2lab1/cpu1_sim/jtag_uart_input_mutex.dat", mutex); if (mutex[0] && !safe) begin // read stream into mem_array after current characters are gone! // save mutex[0] value to compare to address (generates 'safe') mutex[1] <= mutex[0]; // $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]); $readmemb("C:/ece314/nios2lab1/cpu1_sim/jtag_uart_input_stream.dat", mem_array); // bash address and send pulse outside to send the char: address <= 0; pre <= -1; end // else mutex miss... end // poll_count end // reset end // posedge clk //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module jtag_uart_sim_scfifo_r ( // inputs: clk, fifo_rd, rst_n, // outputs: fifo_EF, fifo_rdata, rfifo_full, rfifo_used ) ; output fifo_EF; output [ 7: 0] fifo_rdata; output rfifo_full; output [ 5: 0] rfifo_used; input clk; input fifo_rd; input rst_n; reg [ 31: 0] bytes_left; wire fifo_EF; reg fifo_rd_d; wire [ 7: 0] fifo_rdata; wire new_rom; wire [ 31: 0] num_bytes; wire [ 6: 0] rfifo_entries; wire rfifo_full; wire [ 5: 0] rfifo_used; wire safe; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS //jtag_uart_drom, which is an e_drom jtag_uart_drom_module jtag_uart_drom ( .clk (clk), .incr_addr (fifo_rd_d), .new_rom (new_rom), .num_bytes (num_bytes), .q (fifo_rdata), .reset_n (rst_n), .safe (safe) ); // Generate rfifo_entries for simulation always @(posedge clk or negedge rst_n) begin if (rst_n == 0) begin bytes_left <= 32'h0; fifo_rd_d <= 1'b0; end else begin fifo_rd_d <= fifo_rd; // decrement on read if (fifo_rd_d) bytes_left <= bytes_left - 1'b1; // catch new contents if (new_rom) bytes_left <= num_bytes; end end assign fifo_EF = bytes_left == 32'b0; assign rfifo_full = bytes_left > 7'h40; assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; assign rfifo_used = rfifo_entries[5 : 0]; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module jtag_uart_scfifo_r ( // inputs: clk, fifo_clear, fifo_rd, rst_n, t_dat, wr_rfifo, // outputs: fifo_EF, fifo_rdata, rfifo_full, rfifo_used ) ; output fifo_EF; output [ 7: 0] fifo_rdata; output rfifo_full; output [ 5: 0] rfifo_used; input clk; input fifo_clear; input fifo_rd; input rst_n; input [ 7: 0] t_dat; input wr_rfifo; wire fifo_EF; wire [ 7: 0] fifo_rdata; wire rfifo_full; wire [ 5: 0] rfifo_used; //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS jtag_uart_sim_scfifo_r the_jtag_uart_sim_scfifo_r ( .clk (clk), .fifo_EF (fifo_EF), .fifo_rd (fifo_rd), .fifo_rdata (fifo_rdata), .rfifo_full (rfifo_full), .rfifo_used (rfifo_used), .rst_n (rst_n) ); //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // scfifo rfifo // ( // .aclr (fifo_clear), // .clock (clk), // .data (t_dat), // .empty (fifo_EF), // .full (rfifo_full), // .q (fifo_rdata), // .rdreq (fifo_rd), // .usedw (rfifo_used), // .wrreq (wr_rfifo) // ); // // defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", // rfifo.lpm_numwords = 64, // rfifo.lpm_showahead = "OFF", // rfifo.lpm_type = "scfifo", // rfifo.lpm_width = 8, // rfifo.lpm_widthu = 6, // rfifo.overflow_checking = "OFF", // rfifo.underflow_checking = "OFF", // rfifo.use_eab = "ON"; // //synthesis read_comments_as_HDL off endmodule // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module jtag_uart ( // inputs: av_address, av_chipselect, av_read_n, av_write_n, av_writedata, clk, rst_n, // outputs: av_irq, av_readdata, av_waitrequest, dataavailable, readyfordata ) /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; output av_irq; output [ 31: 0] av_readdata; output av_waitrequest; output dataavailable; output readyfordata; input av_address; input av_chipselect; input av_read_n; input av_write_n; input [ 31: 0] av_writedata; input clk; input rst_n; reg ac; wire activity; wire av_irq; wire [ 31: 0] av_readdata; reg av_waitrequest; reg dataavailable; reg fifo_AE; reg fifo_AF; wire fifo_EF; wire fifo_FF; wire fifo_clear; wire fifo_rd; wire [ 7: 0] fifo_rdata; wire [ 7: 0] fifo_wdata; reg fifo_wr; reg ien_AE; reg ien_AF; wire ipen_AE; wire ipen_AF; reg pause_irq; wire [ 7: 0] r_dat; wire r_ena; reg r_val; wire rd_wfifo; reg read_0; reg readyfordata; wire rfifo_full; wire [ 5: 0] rfifo_used; reg rvalid; reg sim_r_ena; reg sim_t_dat; reg sim_t_ena; reg sim_t_pause; wire [ 7: 0] t_dat; reg t_dav; wire t_ena; wire t_pause; wire wfifo_empty; wire [ 5: 0] wfifo_used; reg woverflow; wire wr_rfifo; //avalon_jtag_slave, which is an e_avalon_slave assign rd_wfifo = r_ena & ~wfifo_empty; assign wr_rfifo = t_ena & ~rfifo_full; assign fifo_clear = ~rst_n; jtag_uart_scfifo_w the_jtag_uart_scfifo_w ( .clk (clk), .fifo_FF (fifo_FF), .fifo_clear (fifo_clear), .fifo_wdata (fifo_wdata), .fifo_wr (fifo_wr), .r_dat (r_dat), .rd_wfifo (rd_wfifo), .wfifo_empty (wfifo_empty), .wfifo_used (wfifo_used) ); jtag_uart_scfifo_r the_jtag_uart_scfifo_r ( .clk (clk), .fifo_EF (fifo_EF), .fifo_clear (fifo_clear), .fifo_rd (fifo_rd), .fifo_rdata (fifo_rdata), .rfifo_full (rfifo_full), .rfifo_used (rfifo_used), .rst_n (rst_n), .t_dat (t_dat), .wr_rfifo (wr_rfifo) ); assign ipen_AE = ien_AE & fifo_AE; assign ipen_AF = ien_AF & (pause_irq | fifo_AF); assign av_irq = ipen_AE | ipen_AF; assign activity = t_pause | t_ena; always @(posedge clk or negedge rst_n) begin if (rst_n == 0) pause_irq <= 1'b0; else // only if fifo is not empty... if (t_pause & ~fifo_EF) pause_irq <= 1'b1; else if (read_0) pause_irq <= 1'b0; end always @(posedge clk or negedge rst_n) begin if (rst_n == 0) begin r_val <= 1'b0; t_dav <= 1'b1; end else begin r_val <= r_ena & ~wfifo_empty; t_dav <= ~rfifo_full; end end always @(posedge clk or negedge rst_n) begin if (rst_n == 0) begin fifo_AE <= 1'b0; fifo_AF <= 1'b0; fifo_wr <= 1'b0; rvalid <= 1'b0; read_0 <= 1'b0; ien_AE <= 1'b0; ien_AF <= 1'b0; ac <= 1'b0; woverflow <= 1'b0; av_waitrequest <= 1'b1; end else begin fifo_AE <= {fifo_FF,wfifo_used} <= 8; fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; fifo_wr <= 1'b0; read_0 <= 1'b0; av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); if (activity) ac <= 1'b1; // write if (av_chipselect & ~av_write_n & av_waitrequest) // addr 1 is control; addr 0 is data if (av_address) begin ien_AF <= av_writedata[0]; ien_AE <= av_writedata[1]; if (av_writedata[10] & ~activity) ac <= 1'b0; end else begin fifo_wr <= ~fifo_FF; woverflow <= fifo_FF; end // read if (av_chipselect & ~av_read_n & av_waitrequest) begin // addr 1 is interrupt; addr 0 is data if (~av_address) rvalid <= ~fifo_EF; read_0 <= ~av_address; end end end assign fifo_wdata = av_writedata[7 : 0]; assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; always @(posedge clk or negedge rst_n) begin if (rst_n == 0) readyfordata <= 0; else if (1) readyfordata <= ~fifo_FF; end //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS // Tie off Atlantic Interface signals not used for simulation always @(posedge clk) begin sim_t_pause <= 1'b0; sim_t_ena <= 1'b0; sim_t_dat <= t_dav ? r_dat : {8{r_val}}; sim_r_ena <= 1'b0; end assign r_ena = sim_r_ena; assign t_ena = sim_t_ena; assign t_dat = sim_t_dat; assign t_pause = sim_t_pause; always @(fifo_EF) begin if (1) dataavailable <= ~fifo_EF; end //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // alt_jtag_atlantic jtag_uart_alt_jtag_atlantic // ( // .clk (clk), // .r_dat (r_dat), // .r_ena (r_ena), // .r_val (r_val), // .rst_n (rst_n), // .t_dat (t_dat), // .t_dav (t_dav), // .t_ena (t_ena), // .t_pause (t_pause) // ); // // defparam jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0, // jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, // jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6; // // always @(posedge clk or negedge rst_n) // begin // if (rst_n == 0) // dataavailable <= 0; // else if (1) // dataavailable <= ~fifo_EF; // end // // //synthesis read_comments_as_HDL off endmodule
onchip_mem.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module onchip_mem ( // inputs: address, byteenable, chipselect, clk, clken, write, writedata, // outputs: readdata ) ; output [ 31: 0] readdata; input [ 12: 0] address; input [ 3: 0] byteenable; input chipselect; input clk; input clken; input write; input [ 31: 0] writedata; wire [ 31: 0] readdata; wire wren; assign wren = chipselect & write; //s1, which is an e_avalon_slave //s2, which is an e_avalon_slave //synthesis translate_off //////////////// SIMULATION-ONLY CONTENTS altsyncram the_altsyncram ( .address_a (address), .byteena_a (byteenable), .clock0 (clk), .clocken0 (clken), .data_a (writedata), .q_a (readdata), .wren_a (wren) ); defparam the_altsyncram.byte_size = 8, the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 8192, the_altsyncram.numwords_a = 8192, the_altsyncram.operation_mode = "SINGLE_PORT", the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO", the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32, the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 13; //////////////// END SIMULATION-ONLY CONTENTS //synthesis translate_on //synthesis read_comments_as_HDL on // altsyncram the_altsyncram // ( // .address_a (address), // .byteena_a (byteenable), // .clock0 (clk), // .clocken0 (clken), // .data_a (writedata), // .q_a (readdata), // .wren_a (wren) // ); // // defparam the_altsyncram.byte_size = 8, // the_altsyncram.init_file = "onchip_mem.hex", // the_altsyncram.lpm_type = "altsyncram", // the_altsyncram.maximum_depth = 8192, // the_altsyncram.numwords_a = 8192, // the_altsyncram.operation_mode = "SINGLE_PORT", // the_altsyncram.outdata_reg_a = "UNREGISTERED", // the_altsyncram.ram_block_type = "AUTO", // the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", // the_altsyncram.width_a = 32, // the_altsyncram.width_byteena_a = 4, // the_altsyncram.widthad_a = 13; // //synthesis read_comments_as_HDL off endmodule
pio.v
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your //use of Altera Corporation's design tools, logic functions and other //software and tools, and its AMPP partner logic functions, and any //output files any of the foregoing (including device programming or //simulation files), and any associated documentation or information are //expressly subject to the terms and conditions of the Altera Program //License Subscription Agreement or other applicable license agreement, //including, without limitation, that your use is for the sole purpose //of programming logic devices manufactured by Altera and sold by Altera //or its authorized distributors. Please refer to the applicable //agreement for further details. // synthesis translate_off `timescale 1ns / 1ps // synthesis translate_on // turn off superfluous verilog processor warnings // altera message_level Level1 // altera message_off 10034 10035 10036 10037 10230 10240 10030 module pio ( // inputs: address, chipselect, clk, in_port, reset_n, write_n, writedata, // outputs: out_port, readdata ) ; output [ 31: 0] out_port; output [ 31: 0] readdata; input [ 1: 0] address; input chipselect; input clk; input [ 31: 0] in_port; input reset_n; input write_n; input [ 31: 0] writedata; wire clk_en; wire [ 31: 0] data_in; reg [ 31: 0] data_out; wire [ 31: 0] out_port; wire [ 31: 0] read_mux_out; reg [ 31: 0] readdata; assign clk_en = 1; //s1, which is an e_avalon_slave assign read_mux_out = {32 {(address == 0)}} & data_in; always @(posedge clk or negedge reset_n) begin if (reset_n == 0) readdata <= 0; else if (clk_en) readdata <= read_mux_out; end always @(posedge clk or negedge reset_n) begin if (reset_n == 0) data_out <= 0; else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[31 : 0]; end assign out_port = data_out; assign data_in = in_port; endmodule
hex_7seg_blanking.v
module hex_7seg_blanking( input [3:0] hex_digit, output [6:0] seg, input blank_in, output blank_out ); reg [6:0] segm; // segm = {g,f,e,d,c,b,a}; // 0 is on and 1 is off always @ (hex_digit) case (hex_digit) 4'h0: segm = ~7'h3F; 4'h1: segm = ~7'h06; // ---a---- 4'h2: segm = ~7'h5B; // | | 4'h3: segm = ~7'h4F; // f b 4'h4: segm = ~7'h66; // | | 4'h5: segm = ~7'h6D; // ---g---- 4'h6: segm = ~7'h7D; // | | 4'h7: segm = ~7'h07; // e c 4'h8: segm = ~7'h7F; // | | 4'h9: segm = ~7'h67; // ---d---- 4'ha: segm = ~7'h77; 4'hb: segm = ~7'h7C; 4'hc: segm = ~7'h39; 4'hd: segm = ~7'h5E; 4'he: segm = ~7'h79; 4'hf: segm = ~7'h71; endcase wire [6:0] blank = ~7'h00; assign blank_out = (hex_digit==4'b0000) && blank_in; assign seg = (blank_out? blank: segm); endmodule
cpu.v
/ Xt`$My<~}A5@%z7FH\0-9EMx*1svGn2uO#)Y>P[!Wn)6ohY[ܾʰ)q3ϺeK^)pHz{%,rU_^^ۜl1An"3"o2ռ$!ژu<LJțZ]$a{V%6SKv$_pWzaY}`5ă_OCS5"Q=X 1W%? |mw>CX ,Jlu|gXi+{~E:tU4 p2--YI-\*@H~VGM]L%|u̾ 4wxF V&-:?%\^j}`~L!@Ű3'|x?qv`Xq"cTe3 6 !Ξ>,Вpj+;tM϶{TU챌rsUmCFM!TOI cfUO7->s."&b*=L`BVFYFQZL0]9A<I"%wB^1AU+(p8a~OՋF~Oܷq54aWYyX3#)TDUM> ˍu ЀȌ)Hҁ 9ÖvAd絩^0W7͊xnjIt7 9nnV%a2[#[x}9#x9XIŤ)./\=ȗ?>(ѭLMsL>!LsxͰjN+kNdnqFt}<m&r%9҇0X|gVD>oh
fit.summary
Fitter Status : Successful - Sat Aug 30 15:00:56 2008 Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Web Edition Revision Name : nios2lab1 Top-level Entity Name : nios2lab1 Family : Cyclone II Device : EP2C35F672C6 Timing Models : Final Total logic elements : 3,122 / 33,216 ( 9 % ) Total combinational functions : 2,770 / 33,216 ( 8 % ) Dedicated logic registers : 1,800 / 33,216 ( 5 % ) Total registers : 1800 Total pins : 182 / 475 ( 38 % ) Total virtual pins : 0 Total memory bits : 325,504 / 483,840 ( 67 % ) Embedded Multiplier 9-bit elements : 4 / 70 ( 6 % ) Total PLLs : 0 / 4 ( 0 % )
tan.summary
-------------------------------------------------------------------------------------- Timing Analyzer Summary -------------------------------------------------------------------------------------- Type : Worst-case tsu Slack : N/A Required Time : None Actual Time : 7.352 ns From : altera_internal_jtag~SHIFTUSER To : cpu1:cpu1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[9] From Clock : -- To Clock : altera_internal_jtag~TCKUTAP Failed Paths : 0 Type : Worst-case tco Slack : N/A Required Time : None Actual Time : 17.824 ns From : cpu1:cpu1|pio:the_pio|data_out[26] To : HEX0[0] From Clock : CLOCK_50 To Clock : -- Failed Paths : 0 Type : Worst-case tpd Slack : N/A Required Time : None Actual Time : 9.882 ns From : SW[16] To : LEDR[16] From Clock : -- To Clock : -- Failed Paths : 0 Type : Worst-case th Slack : N/A Required Time : None Actual Time : 1.868 ns From : altera_internal_jtag~TDIUTAP To : pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|FNUJ6967 From Clock : -- To Clock : altera_internal_jtag~CLKDRUSER Failed Paths : 0 Type : Clock Setup: 'CLOCK_50' Slack : N/A Required Time : None Actual Time : 98.15 MHz ( period = 10.188 ns ) From : cpu1:cpu1|cpu:the_cpu|A_slow_inst_sel To : cpu1:cpu1|cpu:the_cpu|E_src2[24] From Clock : CLOCK_50 To Clock : CLOCK_50 Failed Paths : 0 Type : Clock Setup: 'altera_internal_jtag~TCKUTAP' Slack : N/A Required Time : None Actual Time : 176.06 MHz ( period = 5.680 ns ) From : sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] To : cpu1:cpu1|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[9] From Clock : altera_internal_jtag~TCKUTAP To Clock : altera_internal_jtag~TCKUTAP Failed Paths : 0 Type : Clock Setup: 'altera_internal_jtag~CLKDRUSER' Slack : N/A Required Time : None Actual Time : 458.93 MHz ( period = 2.179 ns ) From : pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[0] To : pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|VELJ8121:JDCF0099|AJQN5180[4] From Clock : altera_internal_jtag~CLKDRUSER To Clock : altera_internal_jtag~CLKDRUSER Failed Paths : 0 Type : Clock Setup: 'altera_internal_jtag~UPDATEUSER' Slack : N/A Required Time : None Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) From : pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[2] To : pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|XWDE0671[0] From Clock : altera_internal_jtag~UPDATEUSER To Clock : altera_internal_jtag~UPDATEUSER Failed Paths : 0 Type : Total number of failed paths Slack : Required Time : Actual Time : From : To : From Clock : To Clock : Failed Paths : 0 --------------------------------------------------------------------------------------
Maintained by John Loomis, last updated Tue Sep 02 20:49:33 2008